On 25/01/2017 9:31 AM, Vitaly Davidovich wrote:
Interesting (not just) Mono bug:
http://www.mono-project.com/news/2016/09/12/arm64-icache/
Scary. From the article's Summary section:
"""
Some ARM big.LITTLE CPUs can have cores with different cache line sizes,
and pretty much no code out there is ready to deal with it as they
assume all cores to be symmetrical.
"""
The article appears to deal with icache flushing. Could multiple cache
line sizes also cause issues for data access? Under what circumstances?
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