Hi, Please find attached a patch for Intel MID DMA driver. This patch fix the DMA Terminate functionalty. This patch has been signed by Vinod Koul the author of the DMA Driver.
Thanks, Selma. >From 638f1b8a5fbb7d4883857ddd70b767dd78f6dfc4 Mon Sep 17 00:00:00 2001 From: Vinod Koul <[email protected]> Date: Tue, 9 Nov 2010 18:33:20 +0100 Subject: [PATCH] DMA: Fix terminate issue Terimate for an active txn was not handled properly, this patch fixes the terminate function to do a proper termination Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Selma Bensaid <[email protected]> --- drivers/dma/intel_mid_dma.c | 19 +++++++++---------- drivers/dma/intel_mid_dma_regs.h | 1 + 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c index 3c0ecc3..c96abd6 100644 --- a/drivers/dma/intel_mid_dma.c +++ b/drivers/dma/intel_mid_dma.c @@ -430,26 +430,25 @@ static int intel_mid_dma_device_control(struct dma_chan *chan, struct middma_device *mid = to_middma_device(chan->device); struct intel_mid_dma_desc *desc, *_desc; LIST_HEAD(list); + union intel_mid_dma_cfg_lo cfg_lo; if (cmd != DMA_TERMINATE_ALL) return -ENXIO; spin_lock_bh(&midc->lock); - if (midc->busy == false) { - spin_unlock_bh(&midc->lock); - return 0; - } - list_splice_init(&midc->free_list, &list); - midc->descs_allocated = 0; - midc->slave = NULL; - + /*Suspend and disable the channel*/ + cfg_lo.cfg_lo = ioread32(midc->ch_regs + CFG_LOW); + cfg_lo.cfgx.ch_susp = 1; + iowrite32(cfg_lo.cfg_lo, midc->ch_regs + CFG_LOW); + iowrite32(DISABLE_CHANNEL(midc->ch_id), mid->dma_base + DMA_CHAN_EN); + midc->busy = false; /* Disable interrupts */ disable_dma_interrupt(midc); spin_unlock_bh(&midc->lock); - list_for_each_entry_safe(desc, _desc, &list, desc_node) { + list_for_each_entry_safe(desc, _desc, &midc->active_list, desc_node) { pr_debug("MDMA: freeing descriptor %p\n", desc); - pci_pool_free(mid->dma_pool, desc, desc->txd.phys); + list_move(&desc->desc_node, &midc->free_list); } return 0; } diff --git a/drivers/dma/intel_mid_dma_regs.h b/drivers/dma/intel_mid_dma_regs.h index a12dd25..8f04a82 100644 --- a/drivers/dma/intel_mid_dma_regs.h +++ b/drivers/dma/intel_mid_dma_regs.h @@ -40,6 +40,7 @@ #define ENABLE_CHANNEL(chan_num) \ ((REG_BIT0 << chan_num) | (REG_BIT8 << chan_num)) +#define DISABLE_CHANNEL(chan_num) (REG_BIT8 << (chan_num)) #define DESCS_PER_CHANNEL 16 /*DMA Registers*/ -- 1.7.2.3 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. NANTERRE Capital: 4,572,000 Euros This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
