>From c0049f1501a79d6d380c83e4421b19d5d83d3679 Mon Sep 17 00:00:00 2001 From: Chuanxiao Dong <[email protected]> Date: Sat, 13 Nov 2010 18:43:50 +0800 Subject: [PATCH 1/3] mmc: get a shared memery address for MFLD sdhci controller
The memery address is shared with SCU. IA and SCU can use this address to indicate who has used the host controller. This shared memery will be only used by the eMMC0 host controller Signed-off-by: Yunpeng Gao <[email protected]> Signed-off-by: Chuanxiao Dong <[email protected]> --- drivers/mmc/host/sdhci-pci.c | 61 +++++++++++++++++++++++++++++++++++++++++- include/linux/mmc/sdhci.h | 11 +++++++- 2 files changed, 70 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index 7bdbd9c..4fc2974 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -43,6 +43,8 @@ #define MAX_SLOTS 8 +#define IPC_EMMC_MUTEX_CMD 0xEE + static DEFINE_MUTEX(port_mutex); struct sdhci_pci_chip; @@ -178,6 +180,55 @@ static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1 = { .probe = mrst_hc1_probe, }; +/* + * Get the base address in shared SRAM for eMMC mutex + * (Dekker's algorithm) through IPC call. + * + * Please note it'll always return 0 whether the address requesting + * success or not. So, the mmc driver will still work well if the scu + * firmware is not ready yet. +*/ +static int mfld_sdio3_probe_slot(struct sdhci_pci_slot *slot) +{ + u32 mutex_var_addr[3]; + int ret; + + ret = intel_scu_ipc_command(IPC_EMMC_MUTEX_CMD, 0, + NULL, 0, mutex_var_addr, 3); + if (ret) { + dev_err(&slot->chip->pdev->dev, "IPC error: %d\n", ret); + slot->host->sram_addr = 0; + } else { + /* 3 housekeeping mutex variables, 12 bytes length */ + slot->host->sram_addr = ioremap_nocache(mutex_var_addr[0], 16); + if (!slot->host->sram_addr) { + dev_err(&slot->chip->pdev->dev, "ioremap failed!\n"); + } else { + dev_info(&slot->chip->pdev->dev, "mapped addr: %p\n", + slot->host->sram_addr); + dev_info(&slot->chip->pdev->dev, "current eMMC owner:" + " %d, IA req: %d, SCU req: %d\n", + readl(slot->host->sram_addr + + DEKKER_EMMC_OWNER_OFFSET), + readl(slot->host->sram_addr + + DEKKER_IA_REQ_OFFSET), + readl(slot->host->sram_addr + + DEKKER_SCU_REQ_OFFSET)); + } + } + + return 0; +} + +static void mfld_sdio3_remove_slot(struct sdhci_pci_slot *slot, int dead) +{ + if (dead) + return; + + if (slot->host->sram_addr) + iounmap(slot->host->sram_addr); +} + static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { .quirks = SDHCI_QUIRK_MFD_SD_RESTRICTION | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, @@ -188,6 +239,14 @@ static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc_sdio = { SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, }; +static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio3 = { + .quirks = SDHCI_QUIRK_NEED_DEKKER_MUTEX | + SDHCI_QUIRK_MFD_EMMC_SDIO_RESTRICTION | + SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .probe_slot = mfld_sdio3_probe_slot, + .remove_slot = mfld_sdio3_remove_slot, +}; + static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) { u8 scratch; @@ -582,7 +641,7 @@ static const struct pci_device_id pci_ids[] __devinitdata = { .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0, .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, - .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc_sdio, + .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio3, }, { diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h index dc712bb..8dec549 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -91,10 +91,19 @@ struct sdhci_host { /* Controller of Medfield specific restriction */ #define SDHCI_QUIRK_MFD_SD_RESTRICTION (1ULL<<33) #define SDHCI_QUIRK_MFD_EMMC_SDIO_RESTRICTION (1ULL<<34) - +/* One controller port will be accessed by driver and fw at the same time */ +#define SDHCI_QUIRK_NEED_DEKKER_MUTEX (1ULL<<35) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ + /* XXX: SCU/X86 mutex variables base address in shared SRAM */ + void __iomem *sram_addr; /* Shared SRAM address */ + +#define DEKKER_EMMC_OWNER_OFFSET 0 +#define DEKKER_IA_REQ_OFFSET 0x04 +#define DEKKER_SCU_REQ_OFFSET 0x08 +#define DEKKER_OWNER_IA 0 +#define DEKKER_OWNER_SCU 1 const struct sdhci_ops *ops; /* Low level hw interface */ -- 1.6.6.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
