Langwell C0 added a new SD host controller. However, SCU fw has not been updated yet to support SD HC2. s0i3 will always be blocked before that is fixed and this patch serves as a workaround before the fw fix is available.
Signed-off-by: Yong Wang <[email protected]> --- arch/x86/platform/mrst/pmu.c | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/platform/mrst/pmu.c b/arch/x86/platform/mrst/pmu.c index 3bd8418..daef72c 100644 --- a/arch/x86/platform/mrst/pmu.c +++ b/arch/x86/platform/mrst/pmu.c @@ -80,6 +80,7 @@ static bool s0i3_pmu_command_pending; static int graphics_is_off; static int lss_s0i3_enabled; +static u32 sdhc2_sss; static struct mrst_device *pci_id_2_mrst_dev(u16 pci_dev_num) { @@ -414,6 +415,10 @@ int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t pci_state) mrst_dev->latest_request = pci_state; /* record latest request */ + if (mrst_dev->lss == LSS_SD_HC2) + sdhc2_sss = SSMSK(pci_2_mrst_state(LSS_SD_HC2, pci_state), + LSS_SD_HC2); + /* * LSS9 and LSS10 contain multiple PCI devices. * Use the lowest numbered (highest power) state in the LSS @@ -459,7 +464,7 @@ int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t pci_state) goto ret; lss_s0i3_enabled = - ((pmu_read_sss() & S0I3_SSS_TARGET) == S0I3_SSS_TARGET); + (((pmu_read_sss() | sdhc2_sss) & S0I3_SSS_TARGET) == S0I3_SSS_TARGET); ret: return status; } @@ -483,7 +488,7 @@ static int pmu_devices_state_show(struct seq_file *s, void *unused) seq_printf(s, "0x%08X D0I1_ACG_SSS_TARGET\n", S0I1_ACG_SSS_TARGET); - cur_pmsss = pmu_read_sss(); + cur_pmsss = (pmu_read_sss() | sdhc2_sss); seq_printf(s, "0x%08X S0I3_SSS_TARGET\n", S0I3_SSS_TARGET); -- 1.5.5.1 _______________________________________________ MeeGo-kernel mailing list [email protected] http://lists.meego.com/listinfo/meego-kernel
