Yves & Lucile Gallot wrote:
> All modern processors use a dynamic execution architecture that blends
> out-of-order and speculative execution with hardware register renaming and
> branch prediction. These processors feature an in-order issue pipeline,
> which breaks processor macroinstructions into simple, micro-operations, and
> an out-of-order, superscalar processor core, which executes the micro-ops.
> The out-of-order core of the processor contains several pipelines to which
> integer, branch, floating-point and memory execution units are attached.
> Many instructions contain few micro-operations then the processor is able to
> execute more than 1 instruction per cycle. Some instructions are complex and
> needs several cycles to be executed (div, sqrt, cos, ...) but they are not
> often used.
> Is that processor a RISC or a CISC ? Neither a RISC nor a CISC! And it is
> really faster than a RISC or a CISC.
Here are a few rules that I use to clearly sort
between RISCs and CISCs:
- orthogonality of the ISA
- no simultaneous mem access and computation
- regular instruction encoding
- single use of MMU.
I don't think that, for instance, the way instructions
are executed or their complexity do matter a lot,
though using these rules you can get some architectural
information.
With these rules (we can add a few others), one can
say in which class a processor falls... But this
thread does not belong to the mailing-list!
Laurent
