> IA64 is really VLIW (very long instruction word), which is quite different
> than traditional sequential RISC. It requires the compiler to do a LOT of
> massively parallel pipeline scheduling to achieve optimal results. HP has
> a
> leg up on this compiler technology as IA64 is based on their existing
> PA-RISC, and is sharing there compiler backend optimzation technology with
> Intel and Microsoft.
>
Intel has some experience with some degree of parallelism dating back to the
i860--which had visible pipelines.
> Having once programmed a VLIW machine in 'assembler', I would not wish
> that
> task on ANYONE. The machine I worked on had 8 parallel asymetrical
> execution units, and a 288 bit wide opcode which launched 8 parallel
> different instructions in every cycle. The assembler (micro?) coder had
> to
> keep track of which parts of what execution unit would take how long to do
> each instruction, and not rely on results before they were ready. To keep
> the machine actually humming along at even close to half its theoretical
> performance levels bordered on nightmarish.
>
Yes, it's not fun at all. I've programmed on the new TI VLIW DSPs and
they're certainly a trip. The things that make this more practical are that
IA64 doesn't have exposed pipelines--*you* don't have to code in pipeline
delays to ensure correct behavior, just decent performance.
You are quite right, though, getting anywhere near even half of theoretical
performance on general purpose VLIW machines for general purpose code is a
monstrous task. DSP is a bit easier as the class of alg. have more self
similarity. *But* this is where we're on the good side of this debate. An
FFT is one of those types of alg.--it has been extensively researched WRT
implementations like this. Intel, I believe, will be providing some
'machine speed' FFT code--if the recent press release is to be believed.
Maybe LL testing code for IA64 will be easier? :)
Cheers,
David
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