On 6 Feb 00, at 18:57, Mikus Grinbergs wrote:
> I seem to recall reading a long long time ago that the positioning
> of variables in real memory was being controlled, to ensure that
> certain cache lines were only being used to hold long-persistence
> variables. (In other words, by placing all short-duration data in
> memory locations that map to OTHER cache lines, the cache lines
> used for long-persistence data would not have to be re-loaded as
> often.)
>
> If this is true, I'm wondering how newer CPU chips affect such a
> scheme. In particular, the Athlon has 64-byte wide cache lines,
> whereas the Pentium had only 32-byte wide cache lines.
Since the page size is 4KB and we're talking about 32 or 64 byte
boundaries, the offset within the page is the same whether we are
considering physical or virtual memory.
Prime95 is known not to be optimized for the Athlon architecture.
However it does seem to run reasonably well.
Actually the cache line issue shouldn't be too important. With luck
you will have pre-loaded some data you're going to need earlier than
you would have done with 32-byte cache lines; in the worst case
you'll simply be ignoring half of the cache line content.
Since the page size is 4KB and we're talking about 32 or 64 byte
boundaries, the offset within the page is the same whether we are
considering physical or virtual memory. In any case, an application
cannot directly control its location in physical memory under any of
the operating systems using a virtual memory scheme.
The optimization that should probably be done for Athlon is to
organize the code to allow FMUL & FADD to execute in parallel (which
the Pentium II/III core just can't manage). This could give a speedup
of the order of 40%.
Regards
Brian Beesley
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