On Wed, 9 Feb 2000 [EMAIL PROTECTED] wrote:
> As I've found the available Athlon documentation (the technical brief
> and the code optimization guide from the AMD website) to be frustratingly
> vague about things like the register set architecture and the functional
> units, can anyone answer the following for me?
That's putting it kindly. AMD's Athlon optimization manual sucks bigtime.
They forget to list the actual freakin' latencies of *any* instructions,
but remember to point out the "industry-leading" and "industry-standard"
features of the chip. I hope I never see these two terms in a technical
manual again.
> 1a,b,c) How many floating-point registers does the Athlon have? Are these
> all 80 bits? Are they accessed via the same kind of stack-based model as
> the Pentium?
>
Apparently the Athlon has three floating point pipelines: 1 FMUL, 1 FADD,
and 1 store pipeline. These split 3DNow and MMX instructions between them
as well as the FPU ones; the only other FPU data we are given is that
there are 88 floating point registers in the register file.
No examples, no stall rules, no latencies, no store bypassing rules, no
decoding rules (for FP) nothing. AMD's K6 family optimization manual was
exactly the same. Lots of luck getting any performance tuning done at all.
It's not even clear that FPU instructions can issue in parallel with
integer instructions (I believe they can, but the two units share the same
three decoders).
I would love for someone to club me over the head and tell me where all
that info is located
jasonp
_________________________________________________________________
Unsubscribe & list info -- http://www.scruz.net/~luke/signup.htm
Mersenne Prime FAQ -- http://www.tasam.com/~lrwiman/FAQ-mers
