George Woltman wrote:
>George is working on it, but is a long way from completion. Progress is
>slow, primarily due to my own laziness. My estimate for a 512K FFT is 0.4
>seconds on a 1.4GHz P4. You can compare that to other machines at
>http://www.mersenne.org/bench.htm.
Jeff Woods wrote:
>Can we assume you meant 0.04?
>
>According to that site, A P-III 1.0 Ghz is already clipping such a number
>at 0.145, and a P4 is already listed there doing such in the current
>version at 0.126....
See, there's afactor of 10 speedup already! :)
Regarding the time estimate of 0.04 seconds per iteration at 512K FFT length,
under optimal load conditions I've gotten around 0.12 sec/iter at this length
with Mlucas running on a 500MHz Alpha 21264 with 4MB L2 cache. This is for
compiled high-level source code, so scaling the closck speed up to 1.4GHz,
subtracting a few tens of % for the smaller caches the L4 will come with
initially, and adding them back for the boost hand-tuned assembly (at least
in George's able hands) tends to yield, 0.04 seconds sounds about right for
what is achievable.
Still, even knowing that the current prototype code is likely quite far
from optimal for the P4, a factor of ~3 speedup (0.126 --> 0.04 seconds)
will be quite a challenge to realize. One of the drawbacks of doing it
by hand in assembler...too bad high-quality HLL compilers (i.e. ones
capable of giving 80-90% of the performance of laboriously coded and
hand-tuned ASM, for complex, data-nonlocal algorithms requiring lots
of data prefetch) appear to be nigh-impossible to write for CISCs like
the x86 family. I don't want to start a RISC-versus-CISC flame war here,
but the fact is, no high-level FFT-based large-integer-multiply code has
gotten within a factor of 2 of the performance of Prime95 on the Pentium.
-Ernst
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