------- Forwarded message follows -------
From:                   "Brian J. Beesley" <[EMAIL PROTECTED]>
To:                     [EMAIL PROTECTED]
Date sent:              Fri, 22 Jun 2001 18:46:43 -0000
Subject:                Re: Mersenne: Factoring on a P4
Copies to:              [EMAIL PROTECTED]

On 22 Jun 2001, at 13:12, [EMAIL PROTECTED] wrote:

> For some reason, I am at a loss to explain, a v21  P4 1.4 GHz
> factors significantely slower that a P3 v20 700MHz.  Is there a
> reason, and solution, for this?

Good question.

AFAIK George has done nothing to the factoring code. You will see a
big "speed loss" if you compare factoring under 2^64 with factoring
over 2^64 on _any_ system - that's simply explained by triple-
precision integer arithmetic being much slower than double-precision
integer arithmetic.

Intel's development for the P4 was very much geared towards making
SSE2 work well. Unfortunately this left less room in the silicon for
some of the "ordinary" integer stuff on which the factoring code (but
not the LL testing code) in Prime95 depends. If memory serves me
right, the 32 bit by 32 bit integer multiply instruction was badly 
hit
by this. Consequently the factoring throughput of a P4 would be
expected to be considerably less than that of a PIII running at the
same clock speed. I would expect that a PIII-700 and a P4-1400 would
probably run factoring at about the same speed.
Earlier I wrote:

For now, those who are lucky enough to have P4 systems are probably
best advised to stick to LL testing (and trial factoring - which will
not be affected by any inefficiency in the P4 integer instructions),
leaving trial factoring to those with slower systems.

Slip of the brain, I'm afraid. I meant "LL testing (and P-1 
factoring..."

Incidentally ECM ought to run pretty well on the P4, though there may 
be some more optimization to come for the very small run lengths 
typically used by ECM.


Regards
Brian Beesley
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