src/mesa/drivers/dri/i915tex/i915_tex_layout.c | 16 +++--- src/mesa/drivers/dri/i915tex/intel_mipmap_tree.c | 59 +++++++++++++++-------- src/mesa/drivers/dri/i915tex/intel_mipmap_tree.h | 10 +++ src/mesa/drivers/dri/i965/brw_tex_layout.c | 4 - src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 - src/mesa/drivers/dri/intel/intel_tex_layout.c | 4 - src/mesa/drivers/dri/intel/intel_tex_layout.h | 2 8 files changed, 64 insertions(+), 36 deletions(-)
commit diffs at http://gitweb.freedesktop.org/?p=mesa/mesa.git;a=summary New commits: commit b9f3f732aaec97aac2a725a4f0b1244ebac61c7f Author: Keith Packard <[EMAIL PROTECTED]> Date: Mon Dec 17 22:43:48 2007 -0800 i915tex: Centralize mipmap pitch computations. mipmap pitches must account for the device alignment requirements, which used to be fairly simple; just align to a 4-byte boundary. However, to allow textures to be drawn to under TTM, they now need to be aligned to a 64-byte boundary. Placing all of the alignment constraints in a single function allows this new constraint to be applied uniformly. There was some pitch constraining code in intel_miptree_create, but that was modifying the pitch long after the miptree had been layed out, so it only served to wreck the mipmap and cause rendering errors. (cherry picked from commit a183efc132c8db1bb42525ac177ffff96f69a59b with manual changes for mesa_7_0_branch by Michel Dänzer. One side effect of this is that i965 also aligns the pitch of 2D textures to multiples of 64 bytes, hopefully that won't cause any issues)
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