Module: Mesa Branch: master Commit: cc13bfbd05934f4053b633627f5bd2ef1108537b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc13bfbd05934f4053b633627f5bd2ef1108537b
Author: Lionel Landwerlin <[email protected]> Date: Sun Feb 2 14:25:16 2020 +0100 intel/genxml: add PIPE_CONTROL command cache invalidate bit This new bit invalidates the cache/prefetch of commands in the command streamer. This will be useful for self modifying batches. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775> --- src/intel/genxml/gen11.xml | 1 + src/intel/genxml/gen12.xml | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index d778abcbfed..5e87d5affc2 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -6272,6 +6272,7 @@ <value name="GGTT" value="1"/> </field> <field name="Flush LLC" start="58" end="58" type="bool"/> + <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/> <field name="Address" start="66" end="111" type="address"/> <field name="Immediate Data" start="128" end="191" type="uint"/> </instruction> diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml index f5ccb182681..b8bada119c2 100644 --- a/src/intel/genxml/gen12.xml +++ b/src/intel/genxml/gen12.xml @@ -6413,6 +6413,7 @@ </field> <field name="Flush LLC" start="58" end="58" type="bool"/> <field name="Tile Cache Flush Enable" start="60" end="60" type="bool"/> + <field name="Command Cache Invalidate Enable" start="61" end="61" type="bool"/> <field name="Address" start="66" end="111" type="address"/> <field name="Immediate Data" start="128" end="191" type="uint"/> </instruction> _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
