Module: Mesa Branch: staging/20.1 Commit: 6550836214af8e3d48c74642a70bcc8b66a6c4da URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6550836214af8e3d48c74642a70bcc8b66a6c4da
Author: Jason Ekstrand <ja...@jlekstrand.net> Date: Fri Jul 17 16:22:11 2020 -0500 intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+ The immediate case is pretty uncommon to see but it can happen, in theory. BROADCAST is typically used to uniformize values and those are usually 32-bit. However, it does come up in some subgroup ops. Fixes: 49c21802cbca "intel/compiler: Split has_64bit_types into float/int" Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6211> (cherry picked from commit cccb497d3c3bbc8f615fe79d774eb42a48e5a95c) --- .pick_status.json | 2 +- src/intel/compiler/brw_eu_emit.c | 18 ++++++++++++++---- src/intel/compiler/brw_fs_generator.cpp | 10 +++++++++- 3 files changed, 24 insertions(+), 6 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index d2ec469daf2..9228a402611 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -112,7 +112,7 @@ "description": "intel/fs: Fix MOV_INDIRECT and BROADCAST of Q types on Gen11+", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": "49c21802cbca8240b272318759b1e472142929e6" }, diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 12042131999..981bb756092 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -3350,9 +3350,18 @@ brw_broadcast(struct brw_codegen *p, * asserting would be mean. */ const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0; - brw_MOV(p, dst, - (align1 ? stride(suboffset(src, i), 0, 1, 0) : - stride(suboffset(src, 4 * i), 0, 4, 1))); + src = align1 ? stride(suboffset(src, i), 0, 1, 0) : + stride(suboffset(src, 4 * i), 0, 4, 1); + + if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) { + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), + subscript(src, BRW_REGISTER_TYPE_D, 0)); + brw_set_default_swsb(p, tgl_swsb_null()); + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), + subscript(src, BRW_REGISTER_TYPE_D, 1)); + } else { + brw_MOV(p, dst, src); + } } else { /* From the Haswell PRM section "Register Region Restrictions": * @@ -3401,7 +3410,8 @@ brw_broadcast(struct brw_codegen *p, /* Use indirect addressing to fetch the specified component. */ if (type_sz(src.type) > 4 && - (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) { + (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) || + !devinfo->has_64bit_float)) { /* From the Cherryview PRM Vol 7. "Register Region Restrictions": * * "When source or destination datatype is 64b or operation is diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 5825e0770d4..34e73cc3ebd 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -410,7 +410,15 @@ fs_generator::generate_mov_indirect(fs_inst *inst, reg.nr = imm_byte_offset / REG_SIZE; reg.subnr = imm_byte_offset % REG_SIZE; - brw_MOV(p, dst, reg); + if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) { + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0), + subscript(reg, BRW_REGISTER_TYPE_D, 0)); + brw_set_default_swsb(p, tgl_swsb_null()); + brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1), + subscript(reg, BRW_REGISTER_TYPE_D, 1)); + } else { + brw_MOV(p, dst, reg); + } } else { /* Prior to Broadwell, there are only 8 address registers. */ assert(inst->exec_size <= 8 || devinfo->gen >= 8); _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
