Module: Mesa Branch: master Commit: b54a0bb528393ba53c5bedf164790d6974627ebf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b54a0bb528393ba53c5bedf164790d6974627ebf
Author: Samuel Iglesias Gonsálvez <[email protected]> Date: Fri Sep 25 13:01:48 2020 +0200 freedreno/layout: add tile_all flag to the layout Added a new tile_all flag which is used to set the TILE_ALL flag of the texture. Enabled tile_all to depth/stencil images are they are non-linear. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jonathan Marek <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6848> --- src/freedreno/fdl/fd6_layout.c | 3 +++ src/freedreno/fdl/freedreno_layout.h | 3 ++- src/freedreno/vulkan/tu_image.c | 10 +++++++--- src/gallium/drivers/freedreno/a6xx/fd6_image.c | 3 ++- src/gallium/drivers/freedreno/a6xx/fd6_texture.c | 5 ++++- 5 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/freedreno/fdl/fd6_layout.c b/src/freedreno/fdl/fd6_layout.c index 096af1672a2..7da7c0ec000 100644 --- a/src/freedreno/fdl/fd6_layout.c +++ b/src/freedreno/fdl/fd6_layout.c @@ -122,6 +122,9 @@ fdl6_layout(struct fdl_layout *layout, if (depth0 > 1 || ubwc_blockwidth == 0) layout->ubwc = false; + if (layout->ubwc || util_format_is_depth_or_stencil(format)) + layout->tile_all = true; + /* in layer_first layout, the level (slice) contains just one * layer (since in fact the layer contains the slices) */ diff --git a/src/freedreno/fdl/freedreno_layout.h b/src/freedreno/fdl/freedreno_layout.h index dc65138be98..494c88f4554 100644 --- a/src/freedreno/fdl/freedreno_layout.h +++ b/src/freedreno/fdl/freedreno_layout.h @@ -102,6 +102,7 @@ struct fdl_layout { uint32_t ubwc_layer_size; /* in bytes */ bool ubwc : 1; bool layer_first : 1; /* see above description */ + bool tile_all : 1; /* Note that for tiled textures, beyond a certain mipmap level (ie. * when width is less than block size) things switch to linear. In @@ -201,7 +202,7 @@ fdl_ubwc_offset(const struct fdl_layout *layout, unsigned level, unsigned layer) static inline bool fdl_level_linear(const struct fdl_layout *layout, int level) { - if (layout->ubwc) + if (layout->tile_all) return false; unsigned w = u_minify(layout->width0, level); diff --git a/src/freedreno/vulkan/tu_image.c b/src/freedreno/vulkan/tu_image.c index 2ee08b72674..51dc897dc94 100644 --- a/src/freedreno/vulkan/tu_image.c +++ b/src/freedreno/vulkan/tu_image.c @@ -454,8 +454,9 @@ tu_image_view_init(struct tu_image_view *iview, format = tu6_plane_format(format, tu6_plane_index(format, aspect_mask)); struct tu_native_format fmt = tu6_format_texture(format, layout->tile_mode); - /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC - * this means smaller mipmap levels have a linear tile mode + /* note: freedreno layout assumes no TILE_ALL bit for non-UBWC color formats + * this means smaller mipmap levels have a linear tile mode. + * Depth/stencil formats have non-linear tile mode. */ fmt.tile_mode = fdl_tile_mode(layout, range->baseMipLevel); @@ -493,6 +494,9 @@ tu_image_view_init(struct tu_image_view *iview, iview->descriptor[4] = base_addr; iview->descriptor[5] = (base_addr >> 32) | A6XX_TEX_CONST_5_DEPTH(depth); + if (layout->tile_all) + iview->descriptor[3] |= A6XX_TEX_CONST_3_TILE_ALL; + if (format == VK_FORMAT_G8_B8R8_2PLANE_420_UNORM || format == VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM) { /* chroma offset re-uses MIPLVLS bits */ @@ -539,7 +543,7 @@ tu_image_view_init(struct tu_image_view *iview, uint32_t block_width, block_height; fdl6_get_ubwc_blockwidth(layout, &block_width, &block_height); - iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL; + iview->descriptor[3] |= A6XX_TEX_CONST_3_FLAG; iview->descriptor[7] = ubwc_addr; iview->descriptor[8] = ubwc_addr >> 32; iview->descriptor[9] |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(layout->ubwc_layer_size >> 2); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_image.c b/src/gallium/drivers/freedreno/a6xx/fd6_image.c index bb65a97f31f..128a15ef21b 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_image.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_image.c @@ -180,7 +180,8 @@ static void emit_image_tex(struct fd_ringbuffer *ring, struct fd6_image *img) A6XX_TEX_CONST_2_TYPE(img->type) | A6XX_TEX_CONST_2_PITCH(img->pitch)); OUT_RING(ring, A6XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch) | - COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL)); + COND(ubwc_enabled, A6XX_TEX_CONST_3_FLAG) | + COND(rsc->layout.tile_all, A6XX_TEX_CONST_3_TILE_ALL)); if (img->bo) { OUT_RELOC(ring, img->bo, img->offset, (uint64_t)A6XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c index 5e6b9010453..e428f751d71 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_texture.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_texture.c @@ -311,11 +311,14 @@ fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc, break; } + if (rsc->layout.tile_all) + so->texconst3 |= A6XX_TEX_CONST_3_TILE_ALL; + if (so->ubwc_enabled) { uint32_t block_width, block_height; fdl6_get_ubwc_blockwidth(&rsc->layout, &block_width, &block_height); - so->texconst3 |= A6XX_TEX_CONST_3_FLAG | A6XX_TEX_CONST_3_TILE_ALL; + so->texconst3 |= A6XX_TEX_CONST_3_FLAG; so->texconst9 |= A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2); so->texconst10 |= A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(fdl_ubwc_pitch(&rsc->layout, lvl)) | _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
