Module: Mesa
Branch: master
Commit: ca40dc01cc8c9b7d5cfda6acf35b1b5e561413d3
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca40dc01cc8c9b7d5cfda6acf35b1b5e561413d3

Author: Marek Olšák <[email protected]>
Date:   Fri Oct  9 18:23:17 2020 -0400

radeonsi: add support for multi draws

Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7056>

---

 src/gallium/drivers/radeonsi/si_state_draw.c | 31 ++++++++++++++++++----------
 1 file changed, 20 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 95945b7a81e..689b7ea06ad 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -950,19 +950,28 @@ static void si_emit_draw_packets(struct si_context *sctx, 
const struct pipe_draw
             return;
          }
 
-         index_va += draws[0].start * index_size;
-
-         radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
-         radeon_emit(cs, index_max_size);
-         radeon_emit(cs, index_va);
-         radeon_emit(cs, index_va >> 32);
-         radeon_emit(cs, draws[0].count);
-         radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+         for (unsigned i = 0; i < num_draws; i++) {
+            uint64_t va = index_va + draws[i].start * index_size;
+
+            radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
+            radeon_emit(cs, index_max_size);
+            radeon_emit(cs, va);
+            radeon_emit(cs, va >> 32);
+            radeon_emit(cs, draws[i].count);
+            radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
+         }
       } else {
-         radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
-         radeon_emit(cs, draws[0].count);
-         radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
+         for (unsigned i = 0; i < num_draws; i++) {
+            if (i > 0)
+               radeon_set_sh_reg(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 
draws[i].start);
+
+            radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
+            radeon_emit(cs, draws[i].count);
+            radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
                             
S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
+         }
+         if (num_draws > 1 && !sctx->num_vs_blit_sgprs)
+            sctx->last_base_vertex = draws[num_draws - 1].start;
       }
    }
 }

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