Module: Mesa Branch: master Commit: 7e412a5d334cde62d07cfd1bec7cdec678a6e0f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e412a5d334cde62d07cfd1bec7cdec678a6e0f6
Author: Vinson Lee <[email protected]> Date: Wed Feb 24 22:11:12 2021 -0800 iris: Fix typos. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Sagar Ghuge <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9382> --- src/gallium/drivers/iris/iris_blorp.c | 2 +- src/gallium/drivers/iris/iris_bufmgr.c | 4 ++-- src/gallium/drivers/iris/iris_bufmgr.h | 2 +- src/gallium/drivers/iris/iris_clear.c | 2 +- src/gallium/drivers/iris/iris_program.c | 2 +- src/gallium/drivers/iris/iris_screen.c | 2 +- src/gallium/drivers/iris/iris_state.c | 2 +- 7 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c index 816db2a9bb6..e887e63e9e1 100644 --- a/src/gallium/drivers/iris/iris_blorp.c +++ b/src/gallium/drivers/iris/iris_blorp.c @@ -275,7 +275,7 @@ iris_blorp_exec(struct blorp_batch *blorp_batch, #endif /* Flush the render cache in cases where the same surface is reinterpreted - * with a differernt format, which blorp does for stencil and depth data + * with a different format, which blorp does for stencil and depth data * among other things. Invalidation of sampler caches and flushing of any * caches which had previously written the source surfaces should already * have been handled by the caller. diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index ce18883adcc..c3391c8f668 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -1048,7 +1048,7 @@ iris_bo_map_cpu(struct pipe_debug_callback *dbg, * contents, and so long as we only read from the CPU mmap we do not * need to write those cachelines back afterwards. * - * On LLC, the emprical evidence suggests that writes from the GPU + * On LLC, the empirical evidence suggests that writes from the GPU * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU * cachelines. (Other reads, such as the display engine, bypass the * LLC entirely requiring us to keep dirty pixels for the scanout @@ -1272,7 +1272,7 @@ iris_bo_wait_rendering(struct iris_bo *bo) * handle. Userspace must make sure this race does not occur if such precision * is important. * - * Note that some kernels have broken the inifite wait for negative values + * Note that some kernels have broken the infinite wait for negative values * promise, upgrade to latest stable kernels if this is the case. */ int diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h index 7755919b9c0..91c03ab35e3 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.h +++ b/src/gallium/drivers/iris/iris_bufmgr.h @@ -170,7 +170,7 @@ struct iris_bo { uint64_t kflags; /** - * Kenel-assigned global name for this object + * Kernel-assigned global name for this object * * List contains both flink named and prime fd'd objects */ diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index a39c92415ab..b61a5c0fc19 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -281,7 +281,7 @@ fast_clear_color(struct iris_context *ice, if (!color_changed && box->depth == 1 && aux_state == ISL_AUX_STATE_CLEAR) return; - /* Ivybrigde PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": + /* Ivybridge PRM Vol 2, Part 1, "11.7 MCS Buffer for Render Target(s)": * * "Any transition from any value in {Clear, Render, Resolve} to a * different value in {Clear, Render, Resolve} requires end of pipe diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index deca44a783a..c973cd843ba 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -810,7 +810,7 @@ iris_setup_binding_table(const struct gen_device_info *devinfo, bt->used_mask[IRIS_SURFACE_GROUP_RENDER_TARGET] = BITFIELD64_MASK(num_render_targets); - /* Setup render target read surface group inorder to support non-coherent + /* Setup render target read surface group in order to support non-coherent * framebuffer fetch on Gen8 */ if (devinfo->gen == 8 && info->outputs_read) { diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index a98ccf29465..97caf234310 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -754,7 +754,7 @@ iris_init_identifier_bo(struct iris_screen *screen) struct pipe_screen * iris_screen_create(int fd, const struct pipe_screen_config *config) { - /* Here are the i915 features we need for Iris (in chronoligical order) : + /* Here are the i915 features we need for Iris (in chronological order) : * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10) * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10) * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 74a75d68826..e805142c1ac 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -387,7 +387,7 @@ flush_before_state_base_change(struct iris_batch *batch) /* Flush before emitting STATE_BASE_ADDRESS. * * This isn't documented anywhere in the PRM. However, it seems to be - * necessary prior to changing the surface state base adress. We've + * necessary prior to changing the surface state base address. We've * seen issues in Vulkan where we get GPU hangs when using multi-level * command buffers which clear depth, reset state base address, and then * go render stuff. _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
