Module: Mesa Branch: master Commit: ee395df3152bffb37f6a358a8b12f5aa613fcf20 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee395df3152bffb37f6a358a8b12f5aa613fcf20
Author: Jason Ekstrand <[email protected]> Date: Mon Mar 15 18:39:19 2021 -0500 genxml: Make 1-bit L3$ config register fields bool on Gen7 Otherwise, they look like booleans but, if you put a value other than 0/1 in them, the GenXML generator code will explode. Fixes: b6875b0094c "anv: Drop has_slm in emit_l3_config for gen11+" Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9614> --- src/intel/genxml/gen7.xml | 14 +++++++------- src/intel/genxml/gen75.xml | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index 255fd5e7eb1..bb59c87a880 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -3768,23 +3768,23 @@ </register> <register name="L3CNTLREG2" length="1" num="0xb020"> - <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="SLM Enable" start="0" end="0" type="bool"/> <field name="URB Allocation" start="1" end="6" type="uint"/> - <field name="URB Low Bandwidth" start="7" end="7" type="uint"/> + <field name="URB Low Bandwidth" start="7" end="7" type="bool"/> <field name="ALL Allocation" start="8" end="13" type="uint"/> <field name="RO Allocation" start="14" end="19" type="uint"/> - <field name="RO Low Bandwidth" start="20" end="20" type="uint"/> + <field name="RO Low Bandwidth" start="20" end="20" type="bool"/> <field name="DC Allocation" start="21" end="26" type="uint"/> - <field name="DC Low Bandwidth" start="27" end="27" type="uint"/> + <field name="DC Low Bandwidth" start="27" end="27" type="bool"/> </register> <register name="L3CNTLREG3" length="1" num="0xb024"> <field name="IS Allocation" start="1" end="6" type="uint"/> - <field name="IS Low Bandwidth" start="7" end="7" type="uint"/> + <field name="IS Low Bandwidth" start="7" end="7" type="bool"/> <field name="C Allocation" start="8" end="13" type="uint"/> - <field name="C Low Bandwidth" start="14" end="14" type="uint"/> + <field name="C Low Bandwidth" start="14" end="14" type="bool"/> <field name="T Allocation" start="15" end="20" type="uint"/> - <field name="T Low Bandwidth" start="21" end="21" type="uint"/> + <field name="T Low Bandwidth" start="21" end="21" type="bool"/> </register> <register name="L3SQCREG1" length="1" num="0xb010"> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index cf7ca7d70de..0d57d7bc795 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -4181,22 +4181,22 @@ </register> <register name="L3CNTLREG2" length="1" num="0xb020"> - <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="SLM Enable" start="0" end="0" type="bool"/> <field name="URB Allocation" start="1" end="6" type="uint"/> - <field name="URB Low Bandwidth" start="7" end="7" type="uint"/> + <field name="URB Low Bandwidth" start="7" end="7" type="bool"/> <field name="RO Allocation" start="14" end="19" type="uint"/> - <field name="RO Low Bandwidth" start="20" end="20" type="uint"/> + <field name="RO Low Bandwidth" start="20" end="20" type="bool"/> <field name="DC Allocation" start="21" end="26" type="uint"/> - <field name="DC Low Bandwidth" start="27" end="27" type="uint"/> + <field name="DC Low Bandwidth" start="27" end="27" type="bool"/> </register> <register name="L3CNTLREG3" length="1" num="0xb024"> <field name="IS Allocation" start="1" end="6" type="uint"/> - <field name="IS Low Bandwidth" start="7" end="7" type="uint"/> + <field name="IS Low Bandwidth" start="7" end="7" type="bool"/> <field name="C Allocation" start="8" end="13" type="uint"/> - <field name="C Low Bandwidth" start="14" end="14" type="uint"/> + <field name="C Low Bandwidth" start="14" end="14" type="bool"/> <field name="T Allocation" start="15" end="20" type="uint"/> - <field name="T Low Bandwidth" start="21" end="21" type="uint"/> + <field name="T Low Bandwidth" start="21" end="21" type="bool"/> </register> <register name="L3SQCREG1" length="1" num="0xb010"> _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
