Module: Mesa Branch: main Commit: 2dc90ca8a442dfecbaca87c531de6d9059f824ec URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2dc90ca8a442dfecbaca87c531de6d9059f824ec
Author: Samuel Pitoiset <[email protected]> Date: Thu Aug 19 08:40:19 2021 +0200 radv: don't use SQ_NON_EVENT before GE_PC_ALLOC for better perf on Navi1x Seems it make the perf worse. Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12466> --- src/amd/vulkan/radv_pipeline.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 43ee8cb9bb6..4bf7a02b243 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1986,12 +1986,6 @@ radv_get_num_input_vertices(nir_shader **nir) static void gfx10_emit_ge_pc_alloc(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t oversub_pc_lines) { - if (chip_class == GFX10) { - /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */ - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); - } - radeon_set_uconfig_reg( cs, R_030980_GE_PC_ALLOC, S_030980_OVERSUB_EN(oversub_pc_lines > 0) | S_030980_NUM_PC_LINES(oversub_pc_lines - 1));
