Module: Mesa Branch: main Commit: d17e75285732878bc3ee8307541c1b4f09cbee7c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d17e75285732878bc3ee8307541c1b4f09cbee7c
Author: Pierre-Eric Pelloux-Prayer <[email protected]> Date: Tue Sep 14 10:57:58 2021 +0200 radeonsi: disable PIPE_CAP_PREFER_BACK_BUFFER_REUSE With https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12763, the DRI_PRIME dGPU -> iGPU copy will be done by the SDMA hw. Since it's asynchronous, it's better to always use at least 2 back buffers to get the next frame rendering started during the copy. Reviewed-by: Marek Olšák <[email protected]> Acked-by: Michel Dänzer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12788> --- src/gallium/drivers/radeonsi/si_get.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 29a3c300981..166102db5f5 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -232,6 +232,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: + case PIPE_CAP_PREFER_BACK_BUFFER_REUSE: return 0; case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
