Module: Mesa Branch: main Commit: e6c6a1afb46df14382f8d9fff7d9b12beea8429d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6c6a1afb46df14382f8d9fff7d9b12beea8429d
Author: Alyssa Rosenzweig <[email protected]> Date: Mon Nov 8 14:43:08 2021 -0500 pan/bi: Fix up dual texturing registers This must be done after RA. How delightful. Use the GenXML strategy to just OR the birds. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723> --- src/panfrost/bifrost/bi_ra.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/panfrost/bifrost/bi_ra.c b/src/panfrost/bifrost/bi_ra.c index 595275b6be6..55bd55eb676 100644 --- a/src/panfrost/bifrost/bi_ra.c +++ b/src/panfrost/bifrost/bi_ra.c @@ -364,6 +364,25 @@ bi_reg_from_index(bi_context *ctx, struct lcra_state *l, bi_index index) return new_index; } +/* Dual texture instructions write to two sets of staging registers, modeled as + * two destinations in the IR. The first set is communicated with the usual + * staging register mechanism. The second set is encoded in the texture + * operation descriptor. This is quite unusual, and requires the following late + * fixup. + */ +static void +bi_fixup_dual_tex_register(bi_instr *I) +{ + assert(I->dest[1].type == BI_INDEX_REGISTER); + assert(I->src[3].type == BI_INDEX_CONSTANT); + + struct bifrost_dual_texture_operation desc = { + .secondary_register = I->dest[1].value + }; + + I->src[3].value |= bi_dual_tex_as_u32(desc); +} + static void bi_install_registers(bi_context *ctx, struct lcra_state *l) { @@ -373,6 +392,9 @@ bi_install_registers(bi_context *ctx, struct lcra_state *l) bi_foreach_src(ins, s) ins->src[s] = bi_reg_from_index(ctx, l, ins->src[s]); + + if (ins->op == BI_OPCODE_TEXC && !bi_is_null(ins->dest[1])) + bi_fixup_dual_tex_register(ins); } }
