Module: Mesa Branch: main Commit: 7876886bdc6910f32d40f454fc369404f2b23d29 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7876886bdc6910f32d40f454fc369404f2b23d29
Author: Daniel Schürmann <[email protected]> Date: Fri Oct 8 13:53:50 2021 +0200 radv: use nir_fold_16bit_sampler_conversions() for now only for texture dest and if there is no rounding mode required. Totals from 2 (0.00% of 150170) affected shaders: (GFX10.3) CodeSize: 7980 -> 7948 (-0.40%) Instrs: 1441 -> 1422 (-1.32%) Latency: 7703 -> 7626 (-1.00%) InvThroughput: 2336 -> 2302 (-1.46%) VClause: 34 -> 36 (+5.88%) Copies: 57 -> 58 (+1.75%) Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592> --- src/amd/vulkan/radv_pipeline.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4ef167c8efa..0baa908684f 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3589,8 +3589,14 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout nir_opt_remove_phis(nir[i]); /* cleanup LCSSA phis */ } if (((nir[i]->info.bit_sizes_int | nir[i]->info.bit_sizes_float) & 16) && - device->physical_device->rad_info.chip_class >= GFX9) + device->physical_device->rad_info.chip_class >= GFX9) { + // TODO: also optimize the tex srcs. see radeonSI for reference */ + /* Skip if there are potentially conflicting rounding modes */ + if (!nir_has_any_rounding_mode_enabled(nir[i]->info.float_controls_execution_mode)) + NIR_PASS_V(nir[i], nir_fold_16bit_sampler_conversions, 0); + NIR_PASS_V(nir[i], nir_opt_vectorize, opt_vectorize_callback, NULL); + } /* cleanup passes */ nir_lower_load_const_to_scalar(nir[i]);
