Module: Mesa Branch: main Commit: 7ae425c5d42776ccbac9bf5481cfc1f1af206bc2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ae425c5d42776ccbac9bf5481cfc1f1af206bc2
Author: Timur Kristóf <[email protected]> Date: Thu Oct 28 21:18:12 2021 +0200 radv: Add support for mesh shading pipelines in the command buffer. - Prefetch mesh shaders - Flush mesh shader descriptors - Assert that input assembly, etc. are ignored. Signed-off-by: Timur Kristóf <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13580> --- src/amd/vulkan/radv_cmd_buffer.c | 37 ++++++++++++++++++++++++++++--------- src/amd/vulkan/radv_private.h | 3 +++ 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 2fbd7d4a6a3..0ae5d068bc1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -47,8 +47,9 @@ enum { RADV_PREFETCH_TES = (1 << 3), RADV_PREFETCH_GS = (1 << 4), RADV_PREFETCH_PS = (1 << 5), + RADV_PREFETCH_MS = (1 << 6), RADV_PREFETCH_SHADERS = (RADV_PREFETCH_VS | RADV_PREFETCH_TCS | RADV_PREFETCH_TES | - RADV_PREFETCH_GS | RADV_PREFETCH_PS) + RADV_PREFETCH_GS | RADV_PREFETCH_PS | RADV_PREFETCH_MS) }; enum { @@ -1096,20 +1097,21 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader static void radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline, - bool vertex_stage_only) + bool first_stage_only) { struct radv_cmd_state *state = &cmd_buffer->state; uint32_t mask = state->prefetch_L2_mask; - if (vertex_stage_only) { - /* Fast prefetch path for starting draws as soon as possible. - */ - mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS | RADV_PREFETCH_VBO_DESCRIPTORS); - } + /* Fast prefetch path for starting draws as soon as possible. */ + if (first_stage_only) + mask &= RADV_PREFETCH_VS | RADV_PREFETCH_VBO_DESCRIPTORS | RADV_PREFETCH_MS; if (mask & RADV_PREFETCH_VS) radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_VERTEX]); + if (mask & RADV_PREFETCH_MS) + radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_MESH]); + if (mask & RADV_PREFETCH_VBO_DESCRIPTORS) si_cp_dma_prefetch(cmd_buffer, state->vb_va, pipeline->vb_desc_alloc_size); @@ -1570,6 +1572,8 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer) { struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; + assert(!cmd_buffer->state.mesh_shading || d->primitive_topology == V_008958_DI_PT_POINTLIST); + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) { radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, d->primitive_topology); @@ -2986,6 +2990,8 @@ radv_emit_vertex_input(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirt struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; struct radv_shader *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX); + assert(!cmd_buffer->state.mesh_shading); + if (!vs_shader->info.vs.has_prolog) return; @@ -3128,6 +3134,10 @@ radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer, radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); + if (radv_pipeline_has_mesh(pipeline)) + radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_MESH, + AC_UD_INDIRECT_DESCRIPTOR_SETS, va); + if (radv_pipeline_has_gs(pipeline)) radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY, AC_UD_INDIRECT_DESCRIPTOR_SETS, va); @@ -3319,6 +3329,9 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_ { if ((pipeline_is_dirty || (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) && cmd_buffer->state.pipeline->vb_desc_usage_mask) { + /* Mesh shaders don't have vertex descriptors. */ + assert(!cmd_buffer->state.mesh_shading); + struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; struct radv_shader *vs_shader = radv_get_shader(pipeline, MESA_SHADER_VERTEX); enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class; @@ -3604,9 +3617,11 @@ radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool { radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty); radv_flush_streamout_descriptors(cmd_buffer); - radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS, cmd_buffer->state.pipeline, + + VkShaderStageFlags stages = VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_MESH_BIT_NV; + radv_flush_descriptors(cmd_buffer, stages, cmd_buffer->state.pipeline, VK_PIPELINE_BIND_POINT_GRAPHICS); - radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS, cmd_buffer->state.pipeline, + radv_flush_constants(cmd_buffer, stages, cmd_buffer->state.pipeline, VK_PIPELINE_BIND_POINT_GRAPHICS); radv_flush_ngg_gs_state(cmd_buffer); } @@ -3769,6 +3784,7 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2KHR sr VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR | + VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV | VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT | VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR)) { cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH; @@ -4504,6 +4520,7 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi cmd_buffer->state.last_sx_blend_opt_control = -1; cmd_buffer->state.last_nggc_settings = -1; cmd_buffer->state.last_nggc_settings_sgpr_idx = -1; + cmd_buffer->state.mesh_shading = false; cmd_buffer->usage_flags = pBeginInfo->flags; if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY && @@ -5028,6 +5045,7 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline if (!pipeline) break; + cmd_buffer->state.mesh_shading = radv_pipeline_has_mesh(pipeline); cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE | RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT; cmd_buffer->push_constant_stages |= pipeline->active_stages; @@ -8282,6 +8300,7 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event, post_index_fetch_flags | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR | + VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV | VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT | VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR | VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR | diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index b1998ea5ffd..14df0e5d53d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1458,6 +1458,9 @@ struct radv_cmd_state { uint32_t last_nggc_settings; int8_t last_nggc_settings_sgpr_idx; bool last_nggc_skip; + + /* Mesh shading state. */ + bool mesh_shading; uint8_t cb_mip[MAX_RTS];
