Module: Mesa Branch: main Commit: 81498f153867c27566d442b7ff64bf8e380902fa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=81498f153867c27566d442b7ff64bf8e380902fa
Author: Alyssa Rosenzweig <[email protected]> Date: Sun Mar 13 14:05:04 2022 -0400 pan/va: Use 64-bit special FAU for pages 1 and 3 This aligns with how the hardware actually sees special FAU. Also fix the names while we're at it. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364> --- src/panfrost/bifrost/valhall/ISA.xml | 36 +++++++++------------- src/panfrost/bifrost/valhall/asm.py | 20 +++++++++--- src/panfrost/bifrost/valhall/disasm.py | 12 +++----- .../bifrost/valhall/test/assembler-cases.txt | 8 ++--- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml index 5c4a46fb3ac..c0fa2c3d9c0 100644 --- a/src/panfrost/bifrost/valhall/ISA.xml +++ b/src/panfrost/bifrost/valhall/ISA.xml @@ -108,16 +108,24 @@ uniforms defined purely in software, Valhall has a some special "constants" passing through data structures. These are encoded like the table of immediates, as if special constant $i$ were lookup table entry - $32 + i$. These special values are selected with the `.ts` modifier. + $32 + i$. </desc> <reserved/> + <value desc="Thread local storage base pointer">thread_local_pointer</value> + <reserved/> + <value desc="Workgroup local storage base pointer">workgroup_local_pointer</value> + <reserved/> + <reserved/> + <reserved/> + <value desc="Shader resource table base pointer">resource_table_pointer</value> + <reserved/> + <reserved/> + <reserved/> + <reserved/> + <reserved/> <reserved/> - <value desc="Thread local storage base pointer (low word)">tls_ptr</value> - <value desc="Thread local storage base pointer (high word)">tls_ptr_hi</value> <reserved/> <reserved/> - <value desc="Workgroup local storage base pointer (low word)">wls_ptr</value> - <value desc="Workgroup local storage base pointer (high word)">wls_ptr_hi</value> </enum> <enum name="Thread identification"> @@ -126,14 +134,11 @@ uniforms defined purely in software, Valhall has a some special "constants" passing through data structures. These are encoded like the table of immediates, as if special constant $i$ were lookup table entry - $32 + i$. These special values are selected with the `.id` modifier. + $32 + i$. </desc> <reserved/> - <reserved/> <value desc="Lane ID">lane_id</value> <reserved/> - <reserved/> - <reserved/> <value desc="Core ID">core_id</value> <reserved/> <reserved/> @@ -146,20 +151,7 @@ <reserved/> <reserved/> <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> - <reserved/> <value desc="Program counter">program_counter</value> - <reserved/> </enum> <enum name="Swizzles (8-bit)"> diff --git a/src/panfrost/bifrost/valhall/asm.py b/src/panfrost/bifrost/valhall/asm.py index 256b7aa46b3..f69325146d5 100644 --- a/src/panfrost/bifrost/valhall/asm.py +++ b/src/panfrost/bifrost/valhall/asm.py @@ -117,11 +117,11 @@ def encode_source(op, fau): elif op[0] == 'i': return int(op[3:]) | 0xC0 elif op in enums['thread_storage_pointers'].bare_values: - idx = 32 + enums['thread_storage_pointers'].bare_values.index(op) + idx = 32 + (enums['thread_storage_pointers'].bare_values.index(op) << 1) fau.set_page(1) return idx | 0xC0 elif op in enums['thread_identification'].bare_values: - idx = 32 + enums['thread_identification'].bare_values.index(op) + idx = 32 + (enums['thread_identification'].bare_values.index(op) << 1) fau.set_page(3) return idx | 0xC0 elif op.startswith('0x'): @@ -241,8 +241,9 @@ def parse_asm(line): for i, (op, src) in enumerate(zip(operands, ins.srcs)): parts = op.split('.') encoded_src = encode_source(parts[0], fau) - encoded |= encoded_src << src.start - fau.push(encoded_src) + + # Require a word selection for special FAU values + needs_word_select = ((encoded_src >> 5) == 0b111) # Has a swizzle been applied yet? swizzled = False @@ -295,6 +296,14 @@ def parse_asm(line): swizzled = True val = enums['lanes_8_bit'].bare_values.index(mod) encoded |= (val << src.offset['widen']) + elif mod in ['w0', 'w1']: + # Chck for special + die_if(not needs_word_select, 'Unexpected word select') + + if mod == 'w1': + encoded_src |= 0x1 + + needs_word_select = False else: die(f"Unknown modifier {mod}") @@ -309,6 +318,9 @@ def parse_asm(line): val = enums['swizzles_16_bit'].bare_values.index(mod) encoded |= (val << src.offset['widen']) + encoded |= encoded_src << src.start + fau.push(encoded_src) + operands = operands[len(ins.srcs):] for i, (op, imm) in enumerate(zip(operands, ins.immediates)): diff --git a/src/panfrost/bifrost/valhall/disasm.py b/src/panfrost/bifrost/valhall/disasm.py index 3996edc3159..3d30a310419 100644 --- a/src/panfrost/bifrost/valhall/disasm.py +++ b/src/panfrost/bifrost/valhall/disasm.py @@ -86,15 +86,11 @@ va_print_src(FILE *fp, uint8_t src, unsigned fau_page) else fprintf(fp, "unk:%X", value); } else if (fau_page == 1) { - if (value < 0x28) - fputs(valhall_thread_storage_pointers[value - 0x20] + 1, fp); - else - fprintf(fp, "unk:%X", value); + fputs(valhall_thread_storage_pointers[(value - 0x20) >> 1] + 1, fp); + fprintf(fp, ".w%u", value & 1); } else if (fau_page == 3) { - if (value < 0x40) - fputs(valhall_thread_identification[value - 0x20] + 1, fp); - else - fprintf(fp, "unk:%X", value); + fputs(valhall_thread_identification[(value - 0x20) >> 1] + 1, fp); + fprintf(fp, ".w%u", value & 1); } else { fprintf(fp, "unk:%X", value); } diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt index c83d88f12af..c256d98d04e 100644 --- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt +++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt @@ -1,9 +1,9 @@ 02 00 00 00 00 c1 91 00 MOV.i32 r1, r2 8a 00 00 00 00 c1 91 00 MOV.i32 r1, u10 -e3 00 00 00 00 c1 91 02 MOV.i32 r1, tls_ptr_hi -e6 00 00 00 00 c1 91 02 MOV.i32 r1, wls_ptr -e2 00 00 00 00 c1 91 06 MOV.i32 r1, lane_id -e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id +e3 00 00 00 00 c1 91 02 MOV.i32 r1, thread_local_pointer.w1 +e6 00 00 00 00 c1 91 02 MOV.i32 r1, workgroup_local_pointer.w0 +e2 00 00 00 00 c1 91 06 MOV.i32 r1, lane_id.w0 +e6 00 00 00 00 c1 91 06 MOV.i32 r1, core_id.w0 01 02 00 00 00 c0 a4 00 FADD.f32 r0, r1, r2 01 02 00 00 20 c0 a4 00 FADD.f32 r0, r1, r2.abs 01 02 00 00 10 c0 a4 00 FADD.f32 r0, r1, r2.neg
