Mesa (staging/22.0): nir_to_tgsi: Fix the address reg mapping for images and SSBOs to match G-T-T.

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Module: Mesa
Branch: staging/22.0
Commit: 77934240580e21eef7fa56231326b3e42f7aafb9
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77934240580e21eef7fa56231326b3e42f7aafb9

Author: Emma Anholt <e...@anholt.net>
Date:   Thu Apr  7 15:26:46 2022 -0700

nir_to_tgsi: Fix the address reg mapping for images and SSBOs to match G-T-T.

I missed these in the previous fix to mimic GLSL-to-TGSI address reg
behavior, which r600 relies on.

Fixes: 4bb9c0a28a5f ("nir_to_tgsi: Use the same address reg mappings as 
GLSL-to-TGSI did.")

Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15824>
(cherry picked from commit e15154a735d8507f45117471f854107442e8a339)

Conflicts:
        src/gallium/auxiliary/nir/nir_to_tgsi.c

---

 .pick_status.json                       |  2 +-
 src/gallium/auxiliary/nir/nir_to_tgsi.c | 14 +++++++-------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 3807658a2ce..4044dc2c96a 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -3284,7 +3284,7 @@
         "description": "nir_to_tgsi: Fix the address reg mapping for images 
and SSBOs to match G-T-T.",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 5,
+        "resolution": 1,
         "because_sha": "4bb9c0a28a5f06341060353dba1a017d154d51a4"
     },
     {
diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c 
b/src/gallium/auxiliary/nir/nir_to_tgsi.c
index ddd6dcdf7da..c0a54541f87 100644
--- a/src/gallium/auxiliary/nir/nir_to_tgsi.c
+++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c
@@ -1245,13 +1245,13 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr 
*instr)
 
 static struct ureg_src
 ntt_ureg_src_indirect(struct ntt_compile *c, struct ureg_src usrc,
-                      nir_src src)
+                      nir_src src, int addr_reg)
 {
    if (nir_src_is_const(src)) {
       usrc.Index += ntt_src_as_uint(c, src);
       return usrc;
    } else {
-      return ureg_src_indirect(usrc, ntt_reladdr(c, ntt_get_src(c, src), 0));
+      return ureg_src_indirect(usrc, ntt_reladdr(c, ntt_get_src(c, src), 
addr_reg));
    }
 }
 
@@ -1412,7 +1412,7 @@ ntt_emit_mem(struct ntt_compile *c, nir_intrinsic_instr 
*instr,
    switch (mode) {
    case nir_var_mem_ssbo:
       memory = ntt_ureg_src_indirect(c, ureg_src_register(TGSI_FILE_BUFFER, 0),
-                                     instr->src[is_store ? 1 : 0]);
+                                     instr->src[is_store ? 1 : 0], 2);
       nir_src = 1;
       break;
    case nir_var_mem_shared:
@@ -1576,7 +1576,7 @@ ntt_emit_image_load_store(struct ntt_compile *c, 
nir_intrinsic_instr *instr)
 
    struct ureg_src resource =
       ntt_ureg_src_indirect(c, ureg_src_register(TGSI_FILE_IMAGE, 0),
-                            instr->src[0]);
+                            instr->src[0], 2);
 
    struct ureg_dst dst;
    if (instr->intrinsic == nir_intrinsic_image_store) {
@@ -1703,18 +1703,18 @@ ntt_emit_load_input(struct ntt_compile *c, 
nir_intrinsic_instr *instr)
 
    switch (instr->intrinsic) {
    case nir_intrinsic_load_input:
-      input = ntt_ureg_src_indirect(c, input, instr->src[0]);
+      input = ntt_ureg_src_indirect(c, input, instr->src[0], 0);
       ntt_store(c, &instr->dest, input);
       break;
 
    case nir_intrinsic_load_per_vertex_input:
-      input = ntt_ureg_src_indirect(c, input, instr->src[1]);
+      input = ntt_ureg_src_indirect(c, input, instr->src[1], 0);
       input = ntt_ureg_src_dimension_indirect(c, input, instr->src[0]);
       ntt_store(c, &instr->dest, input);
       break;
 
    case nir_intrinsic_load_interpolated_input: {
-      input = ntt_ureg_src_indirect(c, input, instr->src[1]);
+      input = ntt_ureg_src_indirect(c, input, instr->src[1], 0);
 
       nir_intrinsic_instr *bary_instr =
          nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr);