Module: Mesa Branch: main Commit: 5a119f15aa7b4fd9033fc298f35cdc89f9217d9c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a119f15aa7b4fd9033fc298f35cdc89f9217d9c
Author: Samuel Pitoiset <[email protected]> Date: Fri May 6 12:39:13 2022 +0200 radv,aco: export alpha-to-coverage via MRTZ on GFX11 Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Rhys Perry <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16369> --- src/amd/compiler/aco_instruction_selection.cpp | 24 ++++++++++++++++++++++++ src/amd/vulkan/radv_pipeline.c | 3 +++ src/amd/vulkan/radv_shader.h | 3 +++ 3 files changed, 30 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 14579b77a0b..91ae43d165a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -10749,6 +10749,23 @@ export_fs_mrt_z(isel_context* ctx) values[1] = Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u]); enabled_channels |= ctx->program->chip_class >= GFX11 ? 0x2 : 0xc; } + + if (ctx->options->key.ps.alpha_to_coverage_via_mrtz && + (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) { + /* MRT0 alpha should be in Y[31:16] if alpha-to-coverage is enabled and MRTZ is present. */ + assert(ctx->program->chip_class >= GFX11); + Operand mrtz_alpha = Operand(ctx->outputs.temps[FRAG_RESULT_DATA0 + 3u]); + mrtz_alpha = + bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand::c32(16u), mrtz_alpha); + if (ctx->program->info.ps.writes_sample_mask) { + /* Ignore the high 16 bits of the sample mask. */ + values[1] = bld.vop3(aco_opcode::v_and_or_b32, bld.def(v1), values[1], + Operand::c32(0x0000ffffu), mrtz_alpha); + } else { + values[1] = mrtz_alpha; + } + enabled_channels |= 0x2; + } } else { if (ctx->program->info.ps.writes_z) { values[0] = Operand(ctx->outputs.temps[FRAG_RESULT_DEPTH * 4u]); @@ -10764,6 +10781,13 @@ export_fs_mrt_z(isel_context* ctx) values[2] = Operand(ctx->outputs.temps[FRAG_RESULT_SAMPLE_MASK * 4u]); enabled_channels |= 0x4; } + + if (ctx->options->key.ps.alpha_to_coverage_via_mrtz && + (ctx->outputs.mask[FRAG_RESULT_DATA0] & 0x8)) { + assert(ctx->program->chip_class >= GFX11); + values[3] = Operand(ctx->outputs.temps[FRAG_RESULT_DATA0 + 3u]); + enabled_channels |= 0x8; + } } /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9021ea297f7..47f132370e6 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3120,6 +3120,9 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline, key.ps.is_int8 = blend->col_format_is_int8; key.ps.is_int10 = blend->col_format_is_int10; } + if (pipeline->device->physical_device->rad_info.chip_class >= GFX11) { + key.ps.alpha_to_coverage_via_mrtz = G_028B70_ALPHA_TO_MASK_ENABLE(blend->db_alpha_to_mask); + } key.vs.topology = vi_info->primitive_topology; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 80364b35a5b..d138323aacf 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -97,6 +97,9 @@ struct radv_pipeline_key { bool lower_discard_to_demote; uint8_t enable_mrt_output_nan_fixup; bool force_vrs_enabled; + + /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */ + bool alpha_to_coverage_via_mrtz; } ps; struct {
