Module: Mesa Branch: main Commit: 9acb30c8c40a86e6f92810e1d149fbf2faeb655b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9acb30c8c40a86e6f92810e1d149fbf2faeb655b
Author: Marcin Ślusarz <[email protected]> Date: Tue Apr 12 15:06:16 2022 +0200 intel/compiler: implement primitive shading rate for mesh Reviewed-by: Caio Oliveira <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16030> --- src/intel/compiler/brw_fs.cpp | 16 ++++++++++----- src/intel/compiler/brw_mesh.cpp | 6 ++++++ .../compiler/brw_nir_lower_shading_rate_output.c | 23 ++++++++++++---------- 3 files changed, 30 insertions(+), 15 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index ee8a922077f..af6c8fbec2a 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -1799,16 +1799,22 @@ calculate_urb_setup(const struct intel_device_info *devinfo, uint64_t per_prim_inputs_read = nir->info.inputs_read & nir->info.per_primitive_inputs; - /* In Mesh, VIEWPORT and LAYER slots are always at the beginning, - * because they come from MUE Primitive Header, not Per-Primitive Attributes. + /* In Mesh, PRIMITIVE_SHADING_RATE, VIEWPORT and LAYER slots + * are always at the beginning, because they come from MUE + * Primitive Header, not Per-Primitive Attributes. */ const uint64_t primitive_header_bits = VARYING_BIT_VIEWPORT | - VARYING_BIT_LAYER; + VARYING_BIT_LAYER | + VARYING_BIT_PRIMITIVE_SHADING_RATE; if (per_prim_inputs_read & primitive_header_bits) { - /* Layer and Viewport live in the same 4-dwords slot (layer - * is dword 1, and viewport is dword 2). + /* Primitive Shading Rate, Layer and Viewport live in the same + * 4-dwords slot (psr is dword 0, layer is dword 1, and viewport + * is dword 2). */ + if (per_prim_inputs_read & VARYING_BIT_PRIMITIVE_SHADING_RATE) + prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_SHADING_RATE] = 0; + if (per_prim_inputs_read & VARYING_BIT_LAYER) prog_data->urb_setup[VARYING_SLOT_LAYER] = 0; diff --git a/src/intel/compiler/brw_mesh.cpp b/src/intel/compiler/brw_mesh.cpp index 92382ea0056..342bf5032eb 100644 --- a/src/intel/compiler/brw_mesh.cpp +++ b/src/intel/compiler/brw_mesh.cpp @@ -362,6 +362,7 @@ brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map) map->per_primitive_header_size_dw = (nir->info.outputs_written & (BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) | BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE) | + BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE) | BITFIELD64_BIT(VARYING_SLOT_LAYER))) ? 8 : 0; map->per_primitive_start_dw = ALIGN(primitive_list_size_dw, 8); @@ -372,6 +373,9 @@ brw_compute_mue_map(struct nir_shader *nir, struct brw_mue_map *map) unsigned start; switch (location) { + case VARYING_SLOT_PRIMITIVE_SHADING_RATE: + start = map->per_primitive_start_dw + 0; + break; case VARYING_SLOT_LAYER: start = map->per_primitive_start_dw + 1; /* RTAIndex */ break; @@ -508,6 +512,8 @@ brw_nir_lower_mue_outputs(nir_shader *nir, const struct brw_mue_map *map) nir_lower_io(nir, nir_var_shader_out, type_size_scalar_dwords, nir_lower_io_lower_64bit_to_32); + + brw_nir_lower_shading_rate_output(nir); } static void diff --git a/src/intel/compiler/brw_nir_lower_shading_rate_output.c b/src/intel/compiler/brw_nir_lower_shading_rate_output.c index 951c78e4c85..fc832b6cba1 100644 --- a/src/intel/compiler/brw_nir_lower_shading_rate_output.c +++ b/src/intel/compiler/brw_nir_lower_shading_rate_output.c @@ -54,17 +54,24 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr, return false; nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - if (intrin->intrinsic != nir_intrinsic_load_output && - intrin->intrinsic != nir_intrinsic_store_output) + nir_intrinsic_op op = intrin->intrinsic; + + if (op != nir_intrinsic_load_output && + op != nir_intrinsic_store_output && + op != nir_intrinsic_load_per_primitive_output && + op != nir_intrinsic_store_per_primitive_output) return false; - if (nir_intrinsic_base(intrin) != VARYING_SLOT_PRIMITIVE_SHADING_RATE) + struct nir_io_semantics io = nir_intrinsic_io_semantics(intrin); + if (io.location != VARYING_SLOT_PRIMITIVE_SHADING_RATE) return false; - b->cursor = intrin->intrinsic == nir_intrinsic_load_output ? - nir_after_instr(instr) : nir_before_instr(instr); + bool is_store = op == nir_intrinsic_store_output || + op == nir_intrinsic_store_per_primitive_output; + + b->cursor = is_store ? nir_before_instr(instr) : nir_after_instr(instr); - if (intrin->intrinsic == nir_intrinsic_store_output) { + if (is_store) { assert(intrin->src[0].is_ssa); nir_ssa_def *bit_field = intrin->src[0].ssa; nir_ssa_def *fp16_x = @@ -80,7 +87,6 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr, nir_instr_rewrite_src(instr, &intrin->src[0], nir_src_for_ssa(packed_fp16_xy)); } else { - assert(intrin->intrinsic == nir_intrinsic_load_output); nir_ssa_def *packed_fp16_xy = &intrin->dest.ssa; nir_ssa_def *u32_x = @@ -102,9 +108,6 @@ lower_shading_rate_output_instr(nir_builder *b, nir_instr *instr, bool brw_nir_lower_shading_rate_output(nir_shader *nir) { - /* TODO(mesh): Add Shading Rate support. */ - assert(nir->info.stage != MESA_SHADER_MESH); - return nir_shader_instructions_pass(nir, lower_shading_rate_output_instr, nir_metadata_block_index | nir_metadata_dominance, NULL);
