Module: Mesa Branch: main Commit: 8fef8ed1b06011c49cd54120011145df3c835a7e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fef8ed1b06011c49cd54120011145df3c835a7e
Author: Mike Blumenkrantz <[email protected]> Date: Thu May 19 19:40:07 2022 -0400 zink: add renderpass bits for color/depth r/w these are different renderpasses according to compatibility rules cc: mesa-stable Reviewed-by: Dave Airlie <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16621> --- src/gallium/drivers/zink/zink_render_pass.c | 6 ++++++ src/gallium/drivers/zink/zink_render_pass.h | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/zink/zink_render_pass.c b/src/gallium/drivers/zink/zink_render_pass.c index 391b553d843..57887b8e062 100644 --- a/src/gallium/drivers/zink/zink_render_pass.c +++ b/src/gallium/drivers/zink/zink_render_pass.c @@ -155,6 +155,12 @@ create_render_pass2(struct zink_screen *screen, struct zink_render_pass_state *s } pstate->num_attachments++; } + if (dep_access & VK_ACCESS_COLOR_ATTACHMENT_READ_BIT) + pstate->color_read = true; + if (dep_access & VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT) + pstate->depth_read = true; + if (dep_access & VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT) + pstate->depth_write = true; if (!screen->info.have_KHR_synchronization2) dep_pipeline = MAX2(dep_pipeline, VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT); diff --git a/src/gallium/drivers/zink/zink_render_pass.h b/src/gallium/drivers/zink/zink_render_pass.h index 7277d4f0a87..32160216cec 100644 --- a/src/gallium/drivers/zink/zink_render_pass.h +++ b/src/gallium/drivers/zink/zink_render_pass.h @@ -65,8 +65,11 @@ struct zink_pipeline_rt { }; struct zink_render_pass_pipeline_state { - uint32_t num_attachments:25; + uint32_t num_attachments:22; uint32_t fbfetch:1; + uint32_t color_read:1; + uint32_t depth_read:1; + uint32_t depth_write:1; uint32_t num_cresolves:4; uint32_t num_zsresolves:1; bool samples:1; //for fs samplemask
