Module: Mesa Branch: main Commit: e6660890827a42698dd5627e1aba0015584c7c22 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6660890827a42698dd5627e1aba0015584c7c22
Author: Lionel Landwerlin <[email protected]> Date: Wed May 25 14:17:03 2022 +0300 intel/disasm: add missing handling of <1;1,0> Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: 7cd9adeb415e ("intel/compiler: In XeHP prefer <1;1,0> regions before compacting") Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16704> --- src/intel/compiler/brw_disasm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 5e0ad96adf8..f87a842e08f 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -1216,6 +1216,7 @@ implied_width(enum brw_vertical_stride _vert_stride, /* "2. Width is equal to vertical stride when Horizontal Stride is zero." */ } else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) { switch (_vert_stride) { + case BRW_VERTICAL_STRIDE_1: return BRW_WIDTH_1; case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2; case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4; case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8;
