Module: Mesa Branch: main Commit: 822e370390e1283f5b8035d1e947b6bb00f677c8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=822e370390e1283f5b8035d1e947b6bb00f677c8
Author: Timur Kristóf <[email protected]> Date: Thu Jun 16 14:42:28 2022 +0200 radv: Allow reusing pipeline compute state emit functions. We are going to reuse them outside of radv_pipeline. Signed-off-by: Timur Kristóf <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16531> --- src/amd/common/ac_gpu_info.c | 5 +++-- src/amd/common/ac_gpu_info.h | 5 +++-- src/amd/vulkan/radv_pipeline.c | 22 ++++++++++------------ src/amd/vulkan/radv_private.h | 6 ++++++ 4 files changed, 22 insertions(+), 16 deletions(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 23bc349998f..1bc3fad778f 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1755,8 +1755,9 @@ void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, } } -unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup, - unsigned max_waves_per_sh, unsigned threadgroups_per_cu) +unsigned +ac_get_compute_resource_limits(const struct radeon_info *info, unsigned waves_per_threadgroup, + unsigned max_waves_per_sh, unsigned threadgroups_per_cu) { unsigned compute_resource_limits = S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index eadd64407b5..a0a2e6286a6 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -259,8 +259,9 @@ void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p); void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, unsigned *cik_raster_config_1_p, unsigned *raster_config_se); -unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup, - unsigned max_waves_per_sh, unsigned threadgroups_per_cu); +unsigned ac_get_compute_resource_limits(const struct radeon_info *info, + unsigned waves_per_threadgroup, unsigned max_waves_per_sh, + unsigned threadgroups_per_cu); struct ac_hs_info { uint32_t tess_offchip_block_dw_size; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 7c610827e8b..62beffc4e74 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -7140,11 +7140,10 @@ radv_CreateGraphicsPipelines(VkDevice _device, VkPipelineCache pipelineCache, ui return result; } -static void -radv_pipeline_emit_hw_cs(struct radeon_cmdbuf *cs, const struct radv_compute_pipeline *pipeline) +void +radv_pipeline_emit_hw_cs(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, + const struct radv_shader *shader) { - const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; - struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE]; uint64_t va = radv_shader_get_va(shader); radeon_set_sh_reg(cs, R_00B830_COMPUTE_PGM_LO, va >> 8); @@ -7157,12 +7156,10 @@ radv_pipeline_emit_hw_cs(struct radeon_cmdbuf *cs, const struct radv_compute_pip } } -static void -radv_pipeline_emit_compute_state(struct radeon_cmdbuf *cs, - const struct radv_compute_pipeline *pipeline) +void +radv_pipeline_emit_compute_state(const struct radv_physical_device *pdevice, + struct radeon_cmdbuf *cs, const struct radv_shader *shader) { - struct radv_physical_device *pdevice = pipeline->base.device->physical_device; - struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE]; unsigned threads_per_threadgroup; unsigned threadgroups_per_cu = 1; unsigned waves_per_threadgroup; @@ -7190,14 +7187,15 @@ radv_pipeline_emit_compute_state(struct radeon_cmdbuf *cs, static void radv_compute_generate_pm4(struct radv_compute_pipeline *pipeline) { - const struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + struct radv_physical_device *pdevice = pipeline->base.device->physical_device; + struct radv_shader *shader = pipeline->base.shaders[MESA_SHADER_COMPUTE]; struct radeon_cmdbuf *cs = &pipeline->base.cs; cs->max_dw = pdevice->rad_info.gfx_level >= GFX10 ? 19 : 16; cs->buf = malloc(cs->max_dw * 4); - radv_pipeline_emit_hw_cs(cs, pipeline); - radv_pipeline_emit_compute_state(cs, pipeline); + radv_pipeline_emit_hw_cs(pdevice, cs, shader); + radv_pipeline_emit_compute_state(pdevice, cs, shader); assert(pipeline->base.cs.cdw <= pipeline->base.cs.max_dw); } diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index aa365a0b6eb..7e9b6f65be1 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2260,6 +2260,12 @@ struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline, struct radv_shader *radv_get_shader(const struct radv_pipeline *pipeline, gl_shader_stage stage); +void radv_pipeline_emit_hw_cs(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, + const struct radv_shader *shader); + +void radv_pipeline_emit_compute_state(const struct radv_physical_device *pdevice, + struct radeon_cmdbuf *cs, const struct radv_shader *shader); + struct radv_graphics_pipeline_create_info { bool use_rectlist; bool db_depth_clear;
