Module: Mesa Branch: main Commit: 42b89276e6f74dfc61a26c16fd10efb2b707b809 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42b89276e6f74dfc61a26c16fd10efb2b707b809
Author: Dylan Baker <[email protected]> Date: Thu Jul 28 13:34:32 2022 -0700 iris|anv: gfx version 12.5 data cache flush is not a workaround This was not a workaround, it was simply missing from the documentation. So remove the workaround language. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17797> --- src/gallium/drivers/iris/iris_clear.c | 10 ++-------- src/intel/vulkan/anv_blorp.c | 10 ++-------- 2 files changed, 4 insertions(+), 16 deletions(-) diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 6391fdb5047..409a0ef7852 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -254,11 +254,6 @@ fast_clear_color(struct iris_context *ice, * and again afterwards to ensure that the resolve is complete before we * do any more regular drawing. */ - - /* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */ - bool data_cache_flush_needed = - intel_device_info_is_dg2(&batch->screen->devinfo); - iris_emit_end_of_pipe_sync(batch, "fast clear: pre-flush", PIPE_CONTROL_RENDER_TARGET_FLUSH | @@ -266,9 +261,8 @@ fast_clear_color(struct iris_context *ice, (devinfo->verx10 == 120 ? PIPE_CONTROL_DEPTH_STALL : 0) | (devinfo->verx10 == 125 ? - PIPE_CONTROL_FLUSH_HDC : 0) | - (data_cache_flush_needed ? - PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | + PIPE_CONTROL_FLUSH_HDC | + PIPE_CONTROL_DATA_CACHE_FLUSH : 0) | PIPE_CONTROL_PSS_STALL_SYNC); iris_batch_sync_region_start(batch); diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 8001f39fdb8..98c59d43899 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1852,20 +1852,14 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer, * resolve and then use a second PIPE_CONTROL after the resolve to ensure * that it is completed before any additional drawing occurs. */ - - /* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */ - bool data_cache_flush_needed = - intel_device_info_is_dg2(&cmd_buffer->device->info); - anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT | (devinfo->verx10 == 120 ? ANV_PIPE_DEPTH_STALL_BIT : 0) | (devinfo->verx10 == 125 ? - ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) | - (data_cache_flush_needed ? - ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | + ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) | ANV_PIPE_PSS_STALL_SYNC_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT, "before fast clear mcs");
