Module: Mesa Branch: main Commit: b3354afd89697fa0a9f249bb7da27ef21d20e53a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3354afd89697fa0a9f249bb7da27ef21d20e53a
Author: Marcin Ślusarz <[email protected]> Date: Sun May 8 02:24:48 2022 +0200 anv: replace VK_SHADER_STAGE_[TASK|MESH]_BIT_NV with VK_SHADER_STAGE_[TASK|MESH]_BIT_EXT They have the same numerical values, so nothing changes. Reviewed-by: Caio Oliveira <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18371> --- src/intel/vulkan/anv_cmd_buffer.c | 12 ++++++------ src/intel/vulkan/anv_device.c | 8 ++++---- src/intel/vulkan/anv_pipeline.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 8 ++++---- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index b3f66f505c7..818572c5d80 100644 --- a/src/intel/vulkan/anv_cmd_buffer.c +++ b/src/intel/vulkan/anv_cmd_buffer.c @@ -483,8 +483,8 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer, stages &= VK_SHADER_STAGE_ALL_GRAPHICS | ((cmd_buffer->device->vk.enabled_extensions.NV_mesh_shader || cmd_buffer->device->vk.enabled_extensions.EXT_mesh_shader) ? - (VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV) : 0); + (VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT) : 0); pipe_state = &cmd_buffer->state.gfx.base; break; @@ -520,8 +520,8 @@ anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer, * This means that we have to upload the descriptor set * as an 64-bit address in the push constants. */ - bool update_desc_sets = stages & (VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV | + bool update_desc_sets = stages & (VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT | VK_SHADER_STAGE_RAYGEN_BIT_KHR | VK_SHADER_STAGE_ANY_HIT_BIT_KHR | VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR | @@ -805,8 +805,8 @@ void anv_CmdPushConstants( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); if (stageFlags & (VK_SHADER_STAGE_ALL_GRAPHICS | - VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV)) { + VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT)) { struct anv_cmd_pipeline_state *pipe_state = &cmd_buffer->state.gfx.base; diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 24c378aa959..585e12decf2 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1894,8 +1894,8 @@ anv_get_physical_device_properties_1_1(struct anv_physical_device *pdevice, } if (pdevice->vk.supported_extensions.NV_mesh_shader || pdevice->vk.supported_extensions.EXT_mesh_shader) { - scalar_stages |= VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV; + scalar_stages |= VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT; } p->subgroupSupportedStages = scalar_stages; p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT | @@ -2042,8 +2042,8 @@ anv_get_physical_device_properties_1_3(struct anv_physical_device *pdevice, p->maxSubgroupSize = 32; p->maxComputeWorkgroupSubgroups = pdevice->info.max_cs_workgroup_threads; p->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT | - VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV; + VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT; p->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE; p->maxPerStageDescriptorInlineUniformBlocks = diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 3b44882baa9..469236f0332 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -1353,7 +1353,7 @@ anv_graphics_pipeline_init_keys(struct anv_graphics_pipeline *pipeline, } assert(pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT || - pipeline->active_stages & VK_SHADER_STAGE_MESH_BIT_NV); + pipeline->active_stages & VK_SHADER_STAGE_MESH_BIT_EXT); } static bool diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 312b83820c8..05855e021b3 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3050,7 +3050,7 @@ cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx; const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline; - if (dirty_stages & VK_SHADER_STAGE_TASK_BIT_NV && + if (dirty_stages & VK_SHADER_STAGE_TASK_BIT_EXT && anv_pipeline_has_stage(pipeline, MESA_SHADER_TASK)) { const struct anv_shader_bin *shader = pipeline->shaders[MESA_SHADER_TASK]; @@ -3073,7 +3073,7 @@ cmd_buffer_flush_mesh_inline_data(struct anv_cmd_buffer *cmd_buffer, } } - if (dirty_stages & VK_SHADER_STAGE_MESH_BIT_NV && + if (dirty_stages & VK_SHADER_STAGE_MESH_BIT_EXT && anv_pipeline_has_stage(pipeline, MESA_SHADER_MESH)) { const struct anv_shader_bin *shader = pipeline->shaders[MESA_SHADER_MESH]; @@ -3570,8 +3570,8 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) dirty & VK_SHADER_STAGE_ALL_GRAPHICS); #if GFX_VERx10 >= 125 cmd_buffer_flush_mesh_inline_data( - cmd_buffer, dirty & (VK_SHADER_STAGE_TASK_BIT_NV | - VK_SHADER_STAGE_MESH_BIT_NV)); + cmd_buffer, dirty & (VK_SHADER_STAGE_TASK_BIT_EXT | + VK_SHADER_STAGE_MESH_BIT_EXT)); #endif }
