URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ffc543b74405d3ddf26fc2f38f844c05530252f
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 17:31:57 2022 +0200
r600/sfn: Use a low number for unused target register
This reduces the number of registers reserved by the shader
units and makes more threads possible.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6856
Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit bf4234d0887d4505f2aae825d23a0144c60e0240)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af62826680f1fc52736dca018bc0c02c0e01c3b6
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 16:21:39 2022 +0200
r600: Fix reporting TGSI IR support
When NIR is not explicitely enabled we still support TGSI.
Fixes: 33765aa92aa5c150873fc210e9d6c1fe22cf8646
r600/sfn: Enable NIR for pre RG hardware
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 90f99369aeccf2a52495319930ff23b8ffa2a691)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7e6466ba7038d669742c675bd281604bf175595
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 15:46:36 2022 +0200
r600/sfn: Use a heuristic to keep SSBO setup and store close
When SSBO instructions use constant address values the address loading
is immediately ready, scheduling the address loads early increases
the register pressure, so force a new instruction block to work around
this problem.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
v2: do handling in shader block to be thread save (hinted to by Filip)
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit c81fe5b235c0204e9f77d13411004a3307aa6301)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c238c91ba4b4a3122704b91797c322f0c3b8f6f
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 15:35:06 2022 +0200
r600/sfn: Don't scan the whole block for ready instructions
Limit the number of tested instructions and the number of
ready instructions that might be taken into account.
This reduces the time needed to run the scheduler significantly.
Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 1f5dccb76057666ff810d889a38e057b078f2448)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20960625393def6674dd4693677c95b09f38eaf5
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 15:30:23 2022 +0200
r600/sfn: Don't schedule GDS instructions early
Atomic GDS instructions like inc, dec, or read will increase the
register pressure, therefore we shouldn't prioritize scheduling them.
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 79eabb81304c0886b723371adfad07ccd7469db5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34e6c8f1569228c4e7ed7f585db7505d992755a2
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 15:03:48 2022 +0200
r600/sfn: Don't tag mem-ring and stream instructions as exports
Export instructions allow burst writes, so it makes send to try
to allocate consecutive registers, but for ring writes we don't
schedule the outputs correctly to exploit this, so for now
don't mark these instructions as export to let the RA restart
picking colors.
When the scheduler starts to emit the ring writes in the right order
to allow for bust writes we might revisit this.
This fixes
[email protected]@execution@variable-indexing@gs-output-array-vec4-index-wr
Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6975
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit fd71cd0b6a068ce4f0187b26d4527c3e1b6dee86)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=45aaf2c6848028002a33b9b596cab72cf2a95e89
Author: Gert Wollny <[email protected]>
Date: Tue Aug 23 09:27:10 2022 +0200
r600/sfn: Handle color0 writes all on R700 like on EG
Fixes: 069f3869ac3a140898224c8c37d5b3b6349361a4
r600/sfn: Fix color outputs when color0 writes all
Signed-off-by: Gert Wollny <[email protected]>
Reviewed-by: Filip Gawin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18212>
(cherry picked from commit 3a0f085837bd605dd5fbd52e4cf934995193e689)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee143bcbee54c06eb96d477836ff201e228c714b
Author: Lucas Stach <[email protected]>
Date: Thu Aug 25 14:16:37 2022 +0200
etnaviv: add debug option to disable linear PE feature
Linear PE has already shown to have some rough corner cases in the hardware
and also has performance implications. Add a debug option to allow to
disable
the feature, so users can more easily check if some issue is caused by this
feature.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <[email protected]>
Reviewed-by: Guido Günther <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 43eb5e777e4b64fe1b143822ae8aaf709eaad42f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69946a64025bfcf25db36b4d9cdd047b0deb566e
Author: Lucas Stach <[email protected]>
Date: Wed Jul 13 19:58:23 2022 +0200
etnaviv: move checking for MC2.0 for TS into screen init
The decision whether to use fast clear aka TS currently checks for two
feature bits: FAST_CEAR and MC20. We check for MC20, as TS on MC1.0 bypasses
the memory offset and we don't have any way to fixup the GPU address to
account for that. It could be done with some support of the kernel driver,
but then GPUs with MC1.0 are very rare to find these days, so not sure if we
are ever going to bother with that.
Instead of checking two separate feature bits to determine if TS can be
used,
mask out the FAST_CLEAR bit from the features when MC20 isn't present. This
way we only have to check for a single feature bit.
CC: mesa-stable #22.2
Signed-off-by: Lucas Stach <[email protected]>
Tested-by: Guido Günther <[email protected]>
Reviewed-by: Guido Günther <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18232>
(cherry picked from commit 09953d7b75524022b5f1e9bfa8264adcfd8691a1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cc636799e750a9b1ba806881169439d4238e592
Author: Kenneth Graunke <[email protected]>
Date: Wed Aug 24 15:11:32 2022 -0700
iris: Use linear for exported resources if we can't convey tiling
If we have modifiers, we can use those to convey the tiling of exported
resources. If we have the deprecated i915 GET/SET_TILING uAPI, we can
use that to convey the tiling.
If we have neither, then we have to fall back to linear.
Fixes: e6588354360 ("iris/bufmgr: Do not use map_gtt or use set/get_tiling
on DG1")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6938
Reviewed-by: Lionel Landwerlin <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18240>
(cherry picked from commit 71ace23fa7ccb27eb4455e38f9254bac5c5b7f86)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8580ce41c605d6b7eb77a972d89bf5fc154cde63
Author: Yiwei Zhang <[email protected]>
Date: Sat Aug 6 05:18:49 2022 +0000
venus: avoid feedback for external fence
Sync fd fence export implies a payload reset operation, and application
can immediately do another submission with the same fence after export.
Concurrent use of the same feedback slot is incorrect. Keeping a list of
feedback slots for sync_fd external fence is a bit over designed given
those fences are usually not checked or waited by the app, but will hand
off the ownership via sync fd to an external client.
Fixes: d7f2e6c8d03 ("venus: add fence feedback")
Signed-off-by: Yiwei Zhang <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
(cherry picked from commit 5457f4c0a497484eca1ecf91af8114f95435c023)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=afb18f4dec6f01e77c9669227541db117fcc54e6
Author: Yiwei Zhang <[email protected]>
Date: Mon Aug 8 18:19:03 2022 +0000
venus: fix external memory ext filtering
Fixes: 390722620e1 ("venus: clean up vn_device_fix_create_info")
Signed-off-by: Yiwei Zhang <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17975>
(cherry picked from commit 9c5a7ffbd8a696182647135ef32bddb347c277f2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f44745add976e0426f85cfbed3bd58dd1504a293
Author: Qiang Yu <[email protected]>
Date: Tue Aug 23 16:14:56 2022 +0800
winsys/amdgpu: fix non-page-aligned sparse buffer creation
ARB_sparse_buffer does not require sparse buffer size to be
page aligned. So we need to align it before VM ops as KMD
will check whether it's aligned and return EINVAL if not.
Fixes: 667da4eaed3 ("winsys/amdgpu: sparse buffer creation / destruction /
commitment")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Qiang Yu <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
(cherry picked from commit 4fc9125ca28bf0b721a18fe8608c693d794d5cab)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bba53989017b435f52d8bad45d589e1eb6e2d50
Author: Eric Engestrom <[email protected]>
Date: Mon Aug 22 21:03:15 2022 +0100
meson: replace manual compiler flags with meson arguments
These would only have worked in GCC and Clang, which so far wasn't an
issue, but let's clean it up anyway.
Cc: mesa-stable
Signed-off-by: Eric Engestrom <[email protected]>
Reviewed-by: Jesse Natalie <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18190>
(cherry picked from commit c66622de3af4efc3717131c55a54b408bc7faade)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad36cf3e4a60e49afd5b8bb9fea5f94f978a999f
Author: Marek Olšák <[email protected]>
Date: Sun Jul 24 20:36:00 2022 -0400
st/mesa: fix potential use-after-free in draw_bitmap_quad
This is super unlikely to be freed before use, but let's fix it anyway.
setup_render_state calls set_sampler_views(take_ownership=true), which
means it takes ownership of the sampler view reference and is free to
unreference it, so we can't use sv after setup_render_state.
Fixes: feda6e9c5d101 - st/mesa: set take_ownership = true in
set_sampler_views
Reviewed-by: Brian Paul <[email protected]>
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
(cherry picked from commit cbad4adc133b16c803ec9445c8dd144bc5023a62)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfc21fbcad2d3d59192d66e89a87dddecba18dd2
Author: Marek Olšák <[email protected]>
Date: Sun Jul 24 19:35:28 2022 -0400
Revert "mesa: implement a display list / glBitmap texture atlas"
This reverts commit b26ddda12fe7dbb6a4e6af3b47c1e837cc7ebb03 and
commit 06d3b0a006f35dc232d512d09f45a6cb4f13cfdf.
Reviewed-by: Brian Paul <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17780>
(cherry picked from commit 6da2fb81a75026d690d856da090cf078fad80ae1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20c3f70dc7939b7b239cde1a687041c2f26b0ab1
Author: Lionel Landwerlin <[email protected]>
Date: Sun Jul 24 13:05:57 2022 +0300
intel/fs: fixup SEND validation check on overlapping src0/src1
With the following SEND instruction :
send(1) nullUD nullUD g0UD
0x4200c504 a0.1<0>UD
This instruction although valid but somewhat nonsensical (SEND message
to write at offset contained in NULL register), triggers an error in
the validator.
The restriction is that we cannot have overlapping sources. The
validator not checking the type of register incorrectly thinks that
the null register (offset 0) is the same as g0.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Rohan Garg <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>
(cherry picked from commit 3c6fa2703dad46a5026cc3993224feff0f106745)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3262b3220fa8563b8193d1b9a710dbe030266504
Author: Mike Blumenkrantz <[email protected]>
Date: Wed Aug 24 08:53:31 2022 -0400
tu: fix invalid free on alloc failure
this is not an allocated pointer
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18230>
(cherry picked from commit 1e7a131fd1ed6d9d1fc338f9387f032ee46a3e33)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23ec1aaf9a92f6831045e9cef356758beef8e82a
Author: Dylan Baker <[email protected]>
Date: Wed Aug 31 10:58:24 2022 -0700
.pick_status.json: Update to 6eb4dfca2344d123c1d7115e68d5a208ebbaba83
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d109d8547f273e963c42aa29a1eec8a4733cca47
Author: Qiang Yu <[email protected]>
Date: Sun Aug 21 15:25:50 2022 +0800
radeonsi: fix tcs_out_lds_offsets arg alignment
tcs_out_lds_offsets is not sure to be 16 byte aligned, it's
calculated like this:
num_patches * patch_vertices * lshs_vertex_stride
num_patches and patch_vertices are not sure to be any value aligned,
lshs_vertex_stride is added one extra dword, so it's only 4 byte
aligned.
This may cause problem even before we switch to nir tess output
lower when write tess factor before read tail of input. But it's
more likely to cause problem after we switch to nir tess output
lower because the main body won't eliminate the low 4bit offset
but epilog will, so they use different offset to read/write tess
factor.
Fixes: 7598bfd768f ("radeonsi: replace llvm tcs output with nir lower pass")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7083
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Qiang Yu <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18174>
(cherry picked from commit ff7c59672fd59c94792b26f7131eb86e57d4b8f4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5126da8cebc4274f81a25c15e9f38002833ab388
Author: Bas Nieuwenhuizen <[email protected]>
Date: Fri Aug 19 14:17:28 2022 +0200
vulkan/wsi: Take max extent into consideration for modifier selection.
For AMD we kinda have some modifiers with a max size ... (Which is
really a compositor/kms issue, but getting them to try kinda falls
into the unsolved "how to allocate/what pitch to use" bucket, so
we solve it on the allocating side)
Cc: mesa-stable
Tested-by: Michel Dänzer <[email protected]>
Reviewed-by: Joshua Ashton <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18139>
(cherry picked from commit bb2a44432400f6c7613905eceb14c6544687ed1f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f708a7240505a40a3f23091c33cb5fbf2113574
Author: Jordan Justen <[email protected]>
Date: Thu Aug 11 01:47:09 2022 -0700
iris: Drop extra file-descriptor dup in iris_drm_screen_create()
In a99e85db9eb, we added a dup into iris_screen_create(). Apparently
some android code paths must be hitting iris_screen_create() without
calling iris_drm_screen_create(). After a99e85db9eb, the code paths
that do hit iris_drm_screen_create() will now dup the fd twice, but
iris_screen_destroy() will only close 1 of these fds.
Fixes: a99e85db9eb ("iris:Duplicate DRM fd internally instead of reuse.")
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Tested-by: Tapani Pälli <[email protected]>
Reviewed-by: José Roberto de Souza <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18020>
(cherry picked from commit e9f40e42de6b47e036d603296ecb5facb384eb0c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e4b17c25547453f281435214ce856bab9af9449
Author: Lionel Landwerlin <[email protected]>
Date: Wed Jun 8 11:04:31 2022 +0300
intel/fs: fixup scratch load/store handling on Gfx12.5+
We did not handle the operation with data size < 4. It works fine on
all other messages (global/shared). The initial commit was just too
restrictive.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 1e242785c315 ("intel/fs: Implement load/store_scratch on XeHP")
Reviewed-by: Caio Oliveira <[email protected]>
Reviewed-by: Ivan Briano <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
(cherry picked from commit 3c78e94ff345fda6314e7644873d960c0ee97dc5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6c42ea33aa25ec192b92f65a47810ba9e2a464b
Author: Lionel Landwerlin <[email protected]>
Date: Thu Jul 7 09:35:38 2022 +0300
intel/fs: fix load_scratch intrinsic
The selection of the internal opcode to deal with load_scratch is
incorrect.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: c6439792287f ("intel/fs: Choose memory message type based on bit
size")
Reviewed-by: Caio Oliveira <[email protected]>
Reviewed-by: Ivan Briano <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16964>
(cherry picked from commit 46a13404c07acdb0412121a6ff55fdbcd5bfea5c)
