Module: Mesa Branch: main Commit: 07a520f73168b1ee49e4baa68751b4e5a4c0d6ab URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07a520f73168b1ee49e4baa68751b4e5a4c0d6ab
Author: Pierre-Eric Pelloux-Prayer <[email protected]> Date: Thu Sep 8 15:43:05 2022 +0200 radeonsi: invalidate L2 when using dcc stores This is only needed on chips with tcc_rb_non_coherent=1. Reviewed-by: Marek Olšák <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7084 Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18494> --- src/gallium/drivers/radeonsi/si_compute_blit.c | 11 +++++++++++ src/gallium/drivers/radeonsi/si_state.c | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index e20d47fb960..48594af13cd 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -209,6 +209,17 @@ static void si_launch_grid_internal(struct si_context *sctx, const struct pipe_g sctx->flags |= sctx->gfx_level <= GFX8 ? SI_CONTEXT_WB_L2 : 0; /* Make sure image stores are visible to all CUs. */ sctx->flags |= SI_CONTEXT_INV_VCACHE; + /* Make sure RBs see our DCC changes. */ + if (sctx->gfx_level >= GFX10 && sctx->screen->info.tcc_rb_non_coherent) { + unsigned enabled_mask = sctx->images[PIPE_SHADER_COMPUTE].enabled_mask; + while (enabled_mask) { + int i = u_bit_scan(&enabled_mask); + if (sctx->images[PIPE_SHADER_COMPUTE].views[i].access & SI_IMAGE_ACCESS_ALLOW_DCC_STORE) { + sctx->flags |= SI_CONTEXT_INV_L2; + break; + } + } + } } else { /* Make sure buffer stores are visible to all CUs. */ sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE | SI_CONTEXT_PFP_SYNC_ME; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index fbee2b6c3f3..3fd29ea5816 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5346,6 +5346,10 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) * automatically at end of shader, but the contents of other * L1 caches might still be stale. */ sctx->flags |= SI_CONTEXT_INV_VCACHE; + + if (flags & (PIPE_BARRIER_IMAGE | PIPE_BARRIER_TEXTURE) && + sctx->screen->info.tcc_rb_non_coherent) + sctx->flags |= SI_CONTEXT_INV_L2; } if (flags & PIPE_BARRIER_INDEX_BUFFER) {
