Module: Mesa Branch: main Commit: d217883c5c33655254b54f32dcac9de046385020 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d217883c5c33655254b54f32dcac9de046385020
Author: Chia-I Wu <[email protected]> Date: Fri Dec 9 11:07:50 2022 -0800 freedreno/a6xx: fix blend all_mrt_write_mask Fix all_mrt_write_mask when independent_blend_enable is false. Otherwise, lrz write is always diabled with MRT when independent_blend_enable is false. This fixes a 2% perf regression for multiple gfxbench benchmarks. Fixes: 0132c22de75 ("freedreno/a6xx: Don't disable LRZ for invalid channels") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20254> --- src/gallium/drivers/freedreno/a6xx/fd6_blend.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c index 7827307f6af..2b49ebd538b 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blend.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blend.c @@ -170,9 +170,9 @@ fd6_blend_state_create(struct pipe_context *pctx, STATIC_ASSERT((4 * PIPE_MAX_COLOR_BUFS) == (8 * sizeof(so->all_mrt_write_mask))); so->all_mrt_write_mask = 0; - unsigned nr = cso->independent_blend_enable ? cso->max_rt : 0; - for (unsigned i = 0; i <= nr; i++) { - const struct pipe_rt_blend_state *rt = &cso->rt[i]; + for (unsigned i = 0; i <= cso->max_rt; i++) { + const struct pipe_rt_blend_state *rt = + &cso->rt[cso->independent_blend_enable ? i : 0]; so->reads_dest |= rt->blend_enable;
