Module: Mesa Branch: main Commit: ec6ad8c7dc069ccbc85a1117b33b2daa9b46b64c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec6ad8c7dc069ccbc85a1117b33b2daa9b46b64c
Author: Rohan Garg <[email protected]> Date: Wed Jan 18 16:00:24 2023 +0100 iris: Don't flush the render cache for a compute batch Make sure we comply with BSpec and ensure that certain flush flags are not set for compute batches Signed-off-by: Rohan Garg's avatarRohan Garg <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15664> --- src/gallium/drivers/iris/iris_context.h | 12 ++++++++++++ src/gallium/drivers/iris/iris_fine_fence.c | 3 +++ src/gallium/drivers/iris/iris_pipe_control.c | 26 ++++++++++++++++++++++---- src/gallium/drivers/iris/iris_query.c | 15 +++++++++++++-- src/gallium/drivers/iris/iris_state.c | 2 +- 5 files changed, 51 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 39f259c3168..af447fb98fc 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -379,6 +379,18 @@ enum pipe_control_flags (PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE | \ PIPE_CONTROL_CONST_CACHE_INVALIDATE) +#define PIPE_CONTROL_GRAPHICS_BITS \ + (PIPE_CONTROL_RENDER_TARGET_FLUSH | \ + PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ + PIPE_CONTROL_TILE_CACHE_FLUSH | \ + PIPE_CONTROL_DEPTH_STALL | \ + PIPE_CONTROL_STALL_AT_SCOREBOARD | \ + PIPE_CONTROL_PSS_STALL_SYNC | \ + PIPE_CONTROL_VF_CACHE_INVALIDATE | \ + PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET | \ + PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE |\ + PIPE_CONTROL_WRITE_DEPTH_COUNT) + enum iris_predicate_state { /* The first two states are used if we can determine whether to draw * without having to look at the values in the query object buffer. This diff --git a/src/gallium/drivers/iris/iris_fine_fence.c b/src/gallium/drivers/iris/iris_fine_fence.c index f057a64882f..5ec9fc45780 100644 --- a/src/gallium/drivers/iris/iris_fine_fence.c +++ b/src/gallium/drivers/iris/iris_fine_fence.c @@ -69,6 +69,9 @@ iris_fine_fence_new(struct iris_batch *batch, unsigned flags) PIPE_CONTROL_TILE_CACHE_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_DATA_CACHE_FLUSH; + + if (batch->name == IRIS_BATCH_COMPUTE) + pc &= ~PIPE_CONTROL_GRAPHICS_BITS; } iris_emit_pipe_control_write(batch, "fence: fine", pc, iris_resource_bo(fine->ref.res), diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c index f26d853ae37..bb38282205d 100644 --- a/src/gallium/drivers/iris/iris_pipe_control.c +++ b/src/gallium/drivers/iris/iris_pipe_control.c @@ -313,20 +313,33 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, } if (bits) { + /* Stall-at-scoreboard is not supported by the compute pipeline, use the + * documented sequence of two PIPE_CONTROLs with PIPE_CONTROL_FLUSH_ENABLE + * set in the second PIPE_CONTROL in order to obtain a similar effect. + */ + const bool compute_stall_sequence = batch->name == IRIS_BATCH_COMPUTE && + (bits & PIPE_CONTROL_STALL_AT_SCOREBOARD) && + !(bits & PIPE_CONTROL_CACHE_FLUSH_BITS); + /* Stall-at-scoreboard is not expected to work in combination with other * flush bits. */ if (bits & PIPE_CONTROL_CACHE_FLUSH_BITS) bits &= ~PIPE_CONTROL_STALL_AT_SCOREBOARD; + if (batch->name == IRIS_BATCH_COMPUTE) + bits &= ~PIPE_CONTROL_GRAPHICS_BITS; + /* Emit any required flushes and invalidations. */ - if (bits & all_flush_bits) + if ((bits & all_flush_bits) || compute_stall_sequence) iris_emit_end_of_pipe_sync(batch, "cache tracker: flush", bits & all_flush_bits); - if (bits & ~all_flush_bits) + if ((bits & ~all_flush_bits) || compute_stall_sequence) iris_emit_pipe_control_flush(batch, "cache tracker: invalidate", - bits & ~all_flush_bits); + (bits & ~all_flush_bits) | + (compute_stall_sequence ? + PIPE_CONTROL_FLUSH_ENABLE : 0)); } } @@ -403,9 +416,14 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags) } iris_foreach_batch(ice, batch) { + const unsigned allowed_bits = + batch->name == IRIS_BATCH_COMPUTE ? ~PIPE_CONTROL_GRAPHICS_BITS : ~0u; + if (batch->contains_draw) { iris_batch_maybe_flush(batch, 24); - iris_emit_pipe_control_flush(batch, "API: memory barrier", bits); + iris_emit_pipe_control_flush(batch, + "API: memory barrier", + bits & allowed_bits); } } } diff --git a/src/gallium/drivers/iris/iris_query.c b/src/gallium/drivers/iris/iris_query.c index f03d24fcb21..ac7df8fe821 100644 --- a/src/gallium/drivers/iris/iris_query.c +++ b/src/gallium/drivers/iris/iris_query.c @@ -173,10 +173,21 @@ write_value(struct iris_context *ice, struct iris_query *q, unsigned offset) struct iris_bo *bo = iris_resource_bo(q->query_state_ref.res); if (!iris_is_query_pipelined(q)) { + enum pipe_control_flags flags = PIPE_CONTROL_CS_STALL | + PIPE_CONTROL_STALL_AT_SCOREBOARD; + if (batch->name == IRIS_BATCH_COMPUTE) { + iris_emit_pipe_control_write(batch, + "query: write immediate for compute batches", + PIPE_CONTROL_WRITE_IMMEDIATE, + bo, + offset, + 0ull); + flags = PIPE_CONTROL_FLUSH_ENABLE; + } + iris_emit_pipe_control_flush(batch, "query: non-pipelined snapshot write", - PIPE_CONTROL_CS_STALL | - PIPE_CONTROL_STALL_AT_SCOREBOARD); + flags); q->stalled = true; } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index f28b6e37dd8..c6f61bbe723 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -654,7 +654,7 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline) enum pipe_control_flags flags = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_FLUSH_HDC; - if (pipeline == GPGPU) { + if (pipeline == GPGPU && batch->name == IRIS_BATCH_RENDER) { flags |= PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH; }
