Module: Mesa Branch: main Commit: 58dd9d5134e280302cc5270d7cc5ecdbc49791de URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=58dd9d5134e280302cc5270d7cc5ecdbc49791de
Author: Tapani Pälli <[email protected]> Date: Fri Jan 13 15:52:00 2023 +0200 hasvk: add restrictions for 3DSTATE_RASTER::AntiAliasingEnable Field must be disabled if any render targets have integer format. Cc: mesa-stable Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20671> --- src/intel/vulkan_hasvk/anv_private.h | 15 +++++++++++++++ src/intel/vulkan_hasvk/genX_cmd_buffer.c | 4 ++++ src/intel/vulkan_hasvk/gfx7_cmd_buffer.c | 9 ++++++++- src/intel/vulkan_hasvk/gfx8_cmd_buffer.c | 16 ++++++++++++++-- 4 files changed, 41 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan_hasvk/anv_private.h b/src/intel/vulkan_hasvk/anv_private.h index 80103821633..e53440253c8 100644 --- a/src/intel/vulkan_hasvk/anv_private.h +++ b/src/intel/vulkan_hasvk/anv_private.h @@ -75,6 +75,7 @@ #include "vk_device.h" #include "vk_drm_syncobj.h" #include "vk_enum_defines.h" +#include "vk_format.h" #include "vk_framebuffer.h" #include "vk_graphics_state.h" #include "vk_image.h" @@ -2451,6 +2452,8 @@ struct anv_cmd_graphics_state { uint32_t index_offset; struct vk_sample_locations_state sample_locations; + + bool has_uint_rt; }; enum anv_depth_reg_mode { @@ -2954,6 +2957,18 @@ anv_cmd_buffer_all_color_write_masked(const struct anv_cmd_buffer *cmd_buffer) return true; } +static inline void +anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state) +{ + state->has_uint_rt = false; + for (unsigned a = 0; a < state->color_att_count; a++) { + if (vk_format_is_int(state->color_att[a].vk_format)) { + state->has_uint_rt = true; + break; + } + } +} + #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \ static inline const struct brw_##prefix##_prog_data * \ get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \ diff --git a/src/intel/vulkan_hasvk/genX_cmd_buffer.c b/src/intel/vulkan_hasvk/genX_cmd_buffer.c index 83b27701af6..1e840ef5dcc 100644 --- a/src/intel/vulkan_hasvk/genX_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/genX_cmd_buffer.c @@ -1376,6 +1376,8 @@ genX(BeginCommandBuffer)( inheritance_info->stencilAttachmentFormat; cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS; + + anv_cmd_graphic_state_update_has_uint_rt(gfx); } } @@ -5255,6 +5257,8 @@ void genX(CmdBeginRendering)( } } + anv_cmd_graphic_state_update_has_uint_rt(gfx); + const struct anv_image_view *ds_iview = NULL; const VkRenderingAttachmentInfo *d_att = pRenderingInfo->pDepthAttachment; const VkRenderingAttachmentInfo *s_att = pRenderingInfo->pStencilAttachment; diff --git a/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c b/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c index 55221799f32..45fe9e9c9fc 100644 --- a/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/gfx7_cmd_buffer.c @@ -80,8 +80,15 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) uint32_t ms_rast_mode = genX(ms_rasterization_mode)(pipeline, dynamic_raster_mode); + /* From the Haswell PRM, Volume 2b, documentation for + * 3DSTATE_SF, "Antialiasing Enable": + * + * "This field must be disabled if any of the render targets + * have integer (UINT or SINT) surface format." + */ bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode, - pipeline->line_mode); + pipeline->line_mode) && + !cmd_buffer->state.gfx.has_uint_rt; uint32_t sf_dw[GENX(3DSTATE_SF_length)]; struct GENX(3DSTATE_SF) sf = { diff --git a/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c b/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c index afd29bad80c..c12a5150a23 100644 --- a/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c +++ b/src/intel/vulkan_hasvk/gfx8_cmd_buffer.c @@ -214,8 +214,20 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) pipeline->line_mode, dyn->rs.line.width, &api_mode, &msaa_raster_enable); - bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode, - pipeline->line_mode); + /* From the Browadwell PRM, Volume 2, documentation for + * 3DSTATE_RASTER, "Antialiasing Enable": + * + * "This field must be disabled if any of the render targets + * have integer (UINT or SINT) surface format." + * + * Additionally internal documentation for Gfx12+ states: + * + * "This bit MUST not be set when NUM_MULTISAMPLES > 1 OR + * FORCED_SAMPLE_COUNT > 1." + */ + bool aa_enable = + anv_rasterization_aa_mode(dynamic_raster_mode, pipeline->line_mode) && + !cmd_buffer->state.gfx.has_uint_rt; uint32_t raster_dw[GENX(3DSTATE_RASTER_length)]; struct GENX(3DSTATE_RASTER) raster = {
