Module: Mesa Branch: main Commit: af7bcc0cdc55e4aa531c999092324c63515658f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=af7bcc0cdc55e4aa531c999092324c63515658f1
Author: Chia-I Wu <[email protected]> Date: Wed Feb 8 15:14:55 2023 -0800 freedreno: avoid conditional ib in fd6_emit_tile CP_REG_TEST (or any command that reads registers) is slow on a618 (gen1). Since SQE can early return, we don't necessarily need emit_conditional_ib in fd6_emit_tile. We still CP_REG_TEST twice for load and store when there is no clear. Not sure if we can simply drop emit_conditional_ib instead? glmark2 score goes from 943 to 1067. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21208> --- src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index 38d3f837eb2..22dbb0d11a6 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -1439,11 +1439,7 @@ prepare_tile_fini_ib(struct fd_batch *batch) assert_dt static void fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile) { - if (!use_hw_binning(batch)) { - fd6_emit_ib(batch->gmem, batch->draw); - } else { - emit_conditional_ib(batch, tile, batch->draw); - } + fd6_emit_ib(batch->gmem, batch->draw); if (batch->tile_epilogue) fd6_emit_ib(batch->gmem, batch->tile_epilogue);
