Module: Mesa Branch: main Commit: 494cb2e5cac369e8c2003b18a83d3b92fe6bc044 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=494cb2e5cac369e8c2003b18a83d3b92fe6bc044
Author: Asahi Lina <[email protected]> Date: Wed Feb 22 20:16:01 2023 +0900 asahi: Flush USC caches on the first draw It seems that when batches are submitted back to back, the USC can retain cache contents between them. This causes a problem when the CPU updates a VBO between batches, since some of those updates might not be visible to the USC. Looks like the VDM barrier command with one magic bit set fixes this, so let's try that. Signed-off-by: Asahi Lina <[email protected]> Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21538> --- src/gallium/drivers/asahi/agx_state.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c index 1d8d0de1253..4367ac2cf19 100644 --- a/src/gallium/drivers/asahi/agx_state.c +++ b/src/gallium/drivers/asahi/agx_state.c @@ -2488,8 +2488,6 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info, batch->resolve |= ctx->zs->store; } - batch->any_draws = true; - if (agx_update_vs(ctx)) ctx->dirty |= AGX_DIRTY_VS | AGX_DIRTY_VS_PROG; else if (ctx->stage[PIPE_SHADER_VERTEX].dirty) @@ -2515,6 +2513,7 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info, AGX_VDM_STATE_VERTEX_SHADER_WORD_1_LENGTH + AGX_VDM_STATE_VERTEX_OUTPUTS_LENGTH + AGX_VDM_STATE_VERTEX_UNKNOWN_LENGTH + 4 /* padding */ + + ((!batch->any_draws) ? AGX_VDM_BARRIER_LENGTH : 0) + AGX_INDEX_LIST_LENGTH + AGX_INDEX_LIST_BUFFER_LO_LENGTH + AGX_INDEX_LIST_COUNT_LENGTH + AGX_INDEX_LIST_INSTANCES_LENGTH + AGX_INDEX_LIST_START_LENGTH + AGX_INDEX_LIST_BUFFER_SIZE_LENGTH); @@ -2552,6 +2551,15 @@ agx_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info, out += AGX_VDM_STATE_RESTART_INDEX_LENGTH; } + if (!batch->any_draws) { + agx_pack(out, VDM_BARRIER, cfg) { + cfg.usc_cache_inval = true; + } + out += AGX_VDM_BARRIER_LENGTH; + } + + batch->any_draws = true; + agx_pack(out, INDEX_LIST, cfg) { cfg.primitive = prim; cfg.instance_count_present = true;
