Module: Mesa Branch: main Commit: eaa8c8097cb4f7a11e91f6214972fd236effe100 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaa8c8097cb4f7a11e91f6214972fd236effe100
Author: Jesse Natalie <[email protected]> Date: Mon Mar 27 11:09:57 2023 -0700 dzn: Don't use write-combine memory for cache-coherent UMA Cache coherent UMA implies that the GPU is reading data through the CPU caches. Using write-combined CPU pages for such a system would be bad, since the GPU would then be reading uncached data. One example of such a system is WARP. This significantly improves WARP's performance for some apps (including the CTS). Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22225> --- src/microsoft/vulkan/dzn_device.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/microsoft/vulkan/dzn_device.c b/src/microsoft/vulkan/dzn_device.c index 22b0ea02c76..af7420c0d08 100644 --- a/src/microsoft/vulkan/dzn_device.c +++ b/src/microsoft/vulkan/dzn_device.c @@ -2596,7 +2596,8 @@ dzn_device_memory_create(struct dzn_device *device, ((mem_type->propertyFlags & VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) && !pdevice->architecture.UMA) ? D3D12_MEMORY_POOL_L1 : D3D12_MEMORY_POOL_L0; - if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) { + if ((mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_CACHED_BIT) || + ((mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) && pdevice->architecture.CacheCoherentUMA)) { heap_desc.Properties.CPUPageProperty = D3D12_CPU_PAGE_PROPERTY_WRITE_BACK; } else if (mem_type->propertyFlags & VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT) { heap_desc.Properties.CPUPageProperty = D3D12_CPU_PAGE_PROPERTY_WRITE_COMBINE;
