Module: Mesa Branch: main Commit: 31bfad83ecff8e76e6b6c0801833c55aa157079f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=31bfad83ecff8e76e6b6c0801833c55aa157079f
Author: Qiang Yu <[email protected]> Date: Fri Apr 14 15:47:10 2023 +0800 aco: support 32bit address in nir_load_smem_amd radeonsi uses 32bit address. Reviewed-by: Rhys Perry <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22525> --- src/amd/compiler/aco_instruction_selection.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 7b685c3a95b..0f095006f65 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -7179,6 +7179,12 @@ visit_load_smem(isel_context* ctx, nir_intrinsic_instr* instr) Temp base = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); Temp offset = bld.as_uniform(get_ssa_temp(ctx, instr->src[1].ssa)); + /* If base address is 32bit, convert to 64bit with the high 32bit part. */ + if (base.bytes() == 4) { + base = bld.pseudo(aco_opcode::p_create_vector, bld.def(s2), + base, Operand::c32(ctx->options->address32_hi)); + } + aco_opcode opcode = aco_opcode::s_load_dword; unsigned size = 1;
