Module: Mesa Branch: main Commit: ecd295bb8bfbc4c9d271ee8e8b4330b86876f8c2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecd295bb8bfbc4c9d271ee8e8b4330b86876f8c2
Author: Alyssa Rosenzweig <[email protected]> Date: Tue May 23 10:10:47 2023 -0400 treewide: Avoid nir_lower_regs_to_ssa calls nir_registers are only supposed to be used temporarily. They may be created by a producer, but then must be immediately lowered prior to optimizing the produced shader. They may be created internally by an optimization pass that doesn't want to deal with phis, but that pass needs to lower them back to phis immediately. Finally they may be created when going out-of-SSA if a backend chooses, but that has to happen late. Regardless, there should be no case where a backend sees a shader that comes in with nir_registers needing to be lowered. The two frontend producers of registers (tgsi_to_nir and mesa/st) both call nir_lower_regs_to_ssa to clean up as they should. Some backend (like intel) already depend on this behaviour. There's no need for other backends to call nir_lower_regs_to_ssa too. Drop the pointless calls as a baby step towards replacing nir_register. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23181> --- src/asahi/compiler/agx_compile.c | 1 - src/freedreno/ir3/ir3_nir.c | 1 - src/gallium/auxiliary/nir/nir_to_tgsi.c | 1 - src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c | 1 - src/gallium/drivers/freedreno/a2xx/ir2_nir.c | 1 - src/gallium/drivers/lima/lima_program.c | 1 - src/gallium/drivers/r600/r600_shader.c | 1 - src/gallium/drivers/r600/sfn/sfn_nir.cpp | 1 - src/gallium/drivers/v3d/v3d_program.c | 1 - src/gallium/drivers/vc4/vc4_program.c | 1 - src/gallium/drivers/zink/zink_compiler.c | 2 -- src/nouveau/codegen/nv50_ir_from_nir.cpp | 1 - src/panfrost/compiler/bifrost_compile.c | 1 - src/panfrost/midgard/midgard_compile.c | 2 -- 14 files changed, 16 deletions(-) diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index 90f94d8f06c..c0443955c86 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -2352,7 +2352,6 @@ agx_preprocess_nir(nir_shader *nir, bool support_lod_bias) .allow_fp16 = true, }; - NIR_PASS_V(nir, nir_lower_regs_to_ssa); NIR_PASS_V(nir, nir_lower_idiv, &idiv_options); NIR_PASS_V(nir, nir_lower_frexp); NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL, NULL); diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c index da842e01c5c..cee0c3f555f 100644 --- a/src/freedreno/ir3/ir3_nir.c +++ b/src/freedreno/ir3/ir3_nir.c @@ -356,7 +356,6 @@ ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s) NIR_PASS_V(s, nir_lower_frexp); NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size); - OPT_V(s, nir_lower_regs_to_ssa); OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s); OPT_V(s, nir_lower_tex, &tex_options); diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 1afa52d4ac9..b25eb3b484c 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3774,7 +3774,6 @@ const void *nir_to_tgsi_options(struct nir_shader *s, NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size, (nir_lower_io_options)0); - NIR_PASS_V(s, nir_lower_regs_to_ssa); nir_to_tgsi_lower_txp(s); NIR_PASS_V(s, nir_to_tgsi_lower_tex); diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index 4c3630d7df3..19bae2b9ada 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -1124,7 +1124,6 @@ etna_compile_shader(struct etna_shader_variant *v) NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_uniform, etna_glsl_type_size, (nir_lower_io_options)0); - NIR_PASS_V(s, nir_lower_regs_to_ssa); NIR_PASS_V(s, nir_lower_vars_to_ssa); NIR_PASS_V(s, nir_lower_indirect_derefs, nir_var_all, UINT32_MAX); NIR_PASS_V(s, nir_lower_tex, &(struct nir_lower_tex_options) { .lower_txp = ~0u, .lower_invalid_implicit_lod = true, }); diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c index a6ded4e8fc3..32ec9fd10bd 100644 --- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c +++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c @@ -121,7 +121,6 @@ ir2_optimize_nir(nir_shader *s, bool lower) debug_printf("----------------------\n"); } - OPT_V(s, nir_lower_regs_to_ssa); OPT_V(s, nir_lower_vars_to_ssa); OPT_V(s, nir_lower_indirect_derefs, nir_var_shader_in | nir_var_shader_out, UINT32_MAX); diff --git a/src/gallium/drivers/lima/lima_program.c b/src/gallium/drivers/lima/lima_program.c index 418808afcba..1500db1f045 100644 --- a/src/gallium/drivers/lima/lima_program.c +++ b/src/gallium/drivers/lima/lima_program.c @@ -227,7 +227,6 @@ lima_program_optimize_fs_nir(struct nir_shader *s, NIR_PASS_V(s, nir_lower_fragcoord_wtrans); NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size, 0); - NIR_PASS_V(s, nir_lower_regs_to_ssa); NIR_PASS_V(s, nir_lower_tex, tex_options); NIR_PASS_V(s, lima_nir_lower_txp); diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index c713dcdae84..5587bea9ef7 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -187,7 +187,6 @@ int r600_pipe_shader_create(struct pipe_context *ctx, sel->nir = tgsi_to_nir(sel->tokens, ctx->screen, true); /* Lower int64 ops because we have some r600 built-in shaders that use it */ if (nir_options->lower_int64_options) { - NIR_PASS_V(sel->nir, nir_lower_regs_to_ssa); NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar, r600_lower_to_scalar_instr_filter, NULL); NIR_PASS_V(sel->nir, nir_lower_int64); } diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 04c056b2b82..742ce61ff4b 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -756,7 +756,6 @@ r600_finalize_nir(pipe_screen *screen, void *shader) nir_shader *nir = (nir_shader *)shader; - NIR_PASS_V(nir, nir_lower_regs_to_ssa); const int nir_lower_flrp_mask = 16 | 32 | 64; NIR_PASS_V(nir, nir_lower_flrp, nir_lower_flrp_mask, false); diff --git a/src/gallium/drivers/v3d/v3d_program.c b/src/gallium/drivers/v3d/v3d_program.c index 32f0a7eb03c..82c178ecc4b 100644 --- a/src/gallium/drivers/v3d/v3d_program.c +++ b/src/gallium/drivers/v3d/v3d_program.c @@ -313,7 +313,6 @@ v3d_uncompiled_shader_create(struct pipe_context *pctx, type_size, (nir_lower_io_options)0); } - NIR_PASS(_, s, nir_lower_regs_to_ssa); NIR_PASS(_, s, nir_normalize_cubemap_coords); NIR_PASS(_, s, nir_lower_load_const_to_scalar); diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index 023967fe4f6..3f8b51a95f7 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -2536,7 +2536,6 @@ vc4_shader_state_create(struct pipe_context *pctx, nir_var_shader_in | nir_var_shader_out | nir_var_uniform, type_size, (nir_lower_io_options)0); - NIR_PASS_V(s, nir_lower_regs_to_ssa); NIR_PASS_V(s, nir_normalize_cubemap_coords); NIR_PASS_V(s, nir_lower_load_const_to_scalar); diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index b72ebbbba4d..769a5b58337 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -4835,7 +4835,6 @@ zink_shader_create(struct zink_screen *screen, struct nir_shader *nir, NIR_PASS_V(nir, fixup_io_locations); NIR_PASS_V(nir, lower_basevertex); - NIR_PASS_V(nir, nir_lower_regs_to_ssa); NIR_PASS_V(nir, lower_baseinstance); NIR_PASS_V(nir, lower_sparse); NIR_PASS_V(nir, split_bitfields); @@ -5287,7 +5286,6 @@ zink_shader_tcs_create(struct zink_screen *screen, nir_shader *tes, unsigned ver nir->info.tess.tcs_vertices_out = vertices_per_patch; nir_validate_shader(nir, "created"); - NIR_PASS_V(nir, nir_lower_regs_to_ssa); optimize_nir(nir, NULL); NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL); NIR_PASS_V(nir, nir_convert_from_ssa, true); diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index 3652ef440d7..9ac2f59cdc9 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -3194,7 +3194,6 @@ Converter::run() /* prepare for IO lowering */ NIR_PASS_V(nir, nir_lower_flrp, lower_flrp, false); NIR_PASS_V(nir, nir_opt_deref); - NIR_PASS_V(nir, nir_lower_regs_to_ssa); NIR_PASS_V(nir, nir_lower_vars_to_ssa); /* codegen assumes vec4 alignment for memory */ diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index 44a51f20bd6..44389370e77 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -4736,7 +4736,6 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id) NIR_PASS_V(nir, pan_lower_sample_pos); NIR_PASS_V(nir, nir_lower_bit_size, bi_lower_bit_size, NULL); NIR_PASS_V(nir, nir_lower_64bit_phis); - NIR_PASS_V(nir, nir_lower_regs_to_ssa); NIR_PASS_V(nir, pan_nir_lower_64bit_intrin); NIR_PASS_V(nir, pan_lower_helper_invocation); NIR_PASS_V(nir, nir_lower_int64); diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index ddd83308a68..644a8852417 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -369,10 +369,8 @@ midgard_preprocess_nir(nir_shader *nir, unsigned gpu_id) NIR_PASS_V(nir, pan_nir_lower_64bit_intrin); NIR_PASS_V(nir, nir_lower_frexp); - NIR_PASS_V(nir, midgard_nir_lower_global_load); - NIR_PASS_V(nir, nir_lower_regs_to_ssa); nir_lower_idiv_options idiv_options = { .allow_fp16 = true, };
