Module: Mesa Branch: staging/23.1 Commit: 144ac599c5e50213caabacd841c04f1c67a3c469 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=144ac599c5e50213caabacd841c04f1c67a3c469
Author: Patrick Lerda <[email protected]> Date: Tue Jun 13 15:23:53 2023 +0200 util/blitter: fix util_blitter_clear_buffer() refcnt imbalance Indeed, the vertex state was restored using a specific condition at the util_blitter_restore_vertex_states() level. This change ensures that the condition is the same when the vertex state is saved. The function util_blitter_clear_buffer() is only called by the r600 driver on pre-evergreen gpus. This issue is triggered on a rv770 gpu with "piglit/bin/fbo-1d -auto -fbo" or "piglit/bin/draw_buffers_gles2 -auto -fbo" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: 5f566faa4607 ("radeonsi: don't save and restore vertex buffers and elements for u_blitter") Signed-off-by: Patrick Lerda <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23721> (cherry picked from commit 23c003b88c54e00436b4e2684e6227e79538cf5a) --- .pick_status.json | 2 +- src/gallium/auxiliary/util/u_blitter.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 206da389451..c7f12f3050a 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -112,7 +112,7 @@ "description": "util/blitter: fix util_blitter_clear_buffer() refcnt imbalance", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "5f566faa46078500d0d70f510d3ce3e75d1f6e83" }, diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c index 5552e04c7c4..bed48ee8cb5 100644 --- a/src/gallium/auxiliary/util/u_blitter.c +++ b/src/gallium/auxiliary/util/u_blitter.c @@ -2634,7 +2634,10 @@ void util_blitter_clear_buffer(struct blitter_context *blitter, blitter_check_saved_vertex_states(ctx); blitter_disable_render_cond(ctx); - pipe->set_vertex_buffers(pipe, ctx->base.vb_slot, 1, 0, false, &vb); + if (ctx->base.saved_vertex_buffer.buffer.resource) { + pipe->set_vertex_buffers(pipe, ctx->base.vb_slot, 1, 0, false, &vb); + } + pipe->bind_vertex_elements_state(pipe, ctx->velem_state_readbuf[num_channels-1]); bind_vs_pos_only(ctx, num_channels);
