Module: Mesa Branch: main Commit: 1b40ab21503fdeabb37950a73ac630240331a4ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b40ab21503fdeabb37950a73ac630240331a4ca
Author: Marek Olšák <[email protected]> Date: Wed Jun 7 23:39:57 2023 -0400 radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR we'll be able to remove 1 TCS user data SGPR thanks to this Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517> --- src/gallium/drivers/radeonsi/si_nir_lower_abi.c | 6 +++--- src/gallium/drivers/radeonsi/si_shader_internal.h | 3 ++- src/gallium/drivers/radeonsi/si_state_draw.cpp | 4 ++-- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c index 342b4cb4c39..3beb5746971 100644 --- a/src/gallium/drivers/radeonsi/si_nir_lower_abi.c +++ b/src/gallium/drivers/radeonsi/si_nir_lower_abi.c @@ -367,12 +367,12 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s } case nir_intrinsic_load_patch_vertices_in: if (stage == MESA_SHADER_TESS_CTRL) - replacement = ac_nir_unpack_arg(b, &args->ac, args->tcs_out_lds_layout, 13, 6); + replacement = ac_nir_unpack_arg(b, &args->ac, args->tcs_offchip_layout, 11, 5); else if (stage == MESA_SHADER_TESS_EVAL) { - nir_ssa_def *tmp = ac_nir_unpack_arg(b, &args->ac, args->tcs_offchip_layout, 6, 5); - replacement = nir_iadd_imm(b, tmp, 1); + replacement = ac_nir_unpack_arg(b, &args->ac, args->tcs_offchip_layout, 6, 5); } else unreachable("no nir_load_patch_vertices_in"); + replacement = nir_iadd_imm(b, replacement, 1); break; case nir_intrinsic_load_sample_mask_in: replacement = ac_nir_load_arg(b, &args->ac, args->ac.sample_coverage); diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index 981e7138da7..4ed2256a2e2 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -42,6 +42,8 @@ struct si_shader_args { * [0:5] = the number of patches per threadgroup - 1, max = 63 * # 5 bits * [6:10] = the number of output vertices per patch - 1, max = 31 + * # 5 bits + * [11:15] = the number of input vertices per patch - 1, max = 31 (TCS only) * # 16 bits * [16:31] = the offset of per patch attributes in the buffer in bytes. * 64 outputs are implied by SI_UNIQUE_SLOT_* values. @@ -59,7 +61,6 @@ struct si_shader_args { */ struct ac_arg tcs_out_lds_offsets; /* Layout of TCS outputs / TES inputs: - * [13:18] = gl_PatchVerticesIn, max = 32 * [19:31] = high 13 bits of the 32-bit address of tessellation ring buffers */ struct ac_arg tcs_out_lds_layout; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp index 992cd6cbc17..e2150847743 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.cpp +++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp @@ -797,10 +797,10 @@ void si_update_tess_io_layout_state(struct si_context *sctx) assert((ring_va & u_bit_consecutive(0, 19)) == 0); sctx->tes_offchip_ring_va_sgpr = ring_va; - sctx->tcs_out_layout = (num_tcs_input_cp << 13) | ring_va; + sctx->tcs_out_layout = ring_va; sctx->tcs_out_offsets = ((perpatch_output_offset / 4) << 16); sctx->tcs_offchip_layout = - (num_patches - 1) | ((num_tcs_output_cp - 1) << 6) | + (num_patches - 1) | ((num_tcs_output_cp - 1) << 6) | ((num_tcs_input_cp - 1) << 11) | ((pervertex_output_patch_size * num_patches) << 16); /* Compute the LDS size. */
