Module: Mesa Branch: main Commit: 3f7ea95bc9ed21588876ff166d4bfa94bf0c4230 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f7ea95bc9ed21588876ff166d4bfa94bf0c4230
Author: Samuel Pitoiset <[email protected]> Date: Tue Jun 27 18:18:56 2023 +0200 radv: inline more values in radv_emit_fb_ds_state() These are no longer adjusted. Signed-off-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23887> --- src/amd/vulkan/radv_cmd_buffer.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 27b18789072..449bf68f388 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2799,8 +2799,6 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ VkImageLayout layout) { const struct radv_image *image = iview->image; - uint32_t db_z_info = ds->db_z_info; - uint32_t db_stencil_info = ds->db_stencil_info; uint32_t db_htile_surface = ds->db_htile_surface; uint32_t db_render_control = ds->db_render_control | cmd_buffer->state.db_render_control; @@ -2828,8 +2826,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7); radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1)); } - radeon_emit(cmd_buffer->cs, db_z_info); - radeon_emit(cmd_buffer->cs, db_stencil_info); + radeon_emit(cmd_buffer->cs, ds->db_z_info); + radeon_emit(cmd_buffer->cs, ds->db_stencil_info); radeon_emit(cmd_buffer->cs, ds->db_z_read_base); radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); radeon_emit(cmd_buffer->cs, ds->db_z_read_base); @@ -2848,8 +2846,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ radeon_emit(cmd_buffer->cs, ds->db_depth_size); radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10); - radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */ - radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */ + radeon_emit(cmd_buffer->cs, ds->db_z_info); /* DB_Z_INFO */ + radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* DB_STENCIL_INFO */ radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */ radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32)); /* DB_Z_READ_BASE_HI */ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */ @@ -2867,8 +2865,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9); radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ - radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */ - radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */ + radeon_emit(cmd_buffer->cs, ds->db_z_info); /* R_028040_DB_Z_INFO */ + radeon_emit(cmd_buffer->cs, ds->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */ radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */ radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
