Module: Mesa Branch: main Commit: 3e269c7a4e309a232177bf15a7994ae0270b8627 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e269c7a4e309a232177bf15a7994ae0270b8627
Author: Joshua Ashton <[email protected]> Date: Mon Jul 3 20:23:13 2023 +0100 radv: Rename radv_required_subgroup_info to radv_shader_stage_key Additionally, prefix the members that are subgroup related with subgroup_ We will use this structure to store pipeline robustness information. Signed-off-by: Joshua Ashton <[email protected]> Reviewed-by: Friedrich Vock <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23912> --- src/amd/vulkan/radv_pipeline.c | 6 +++--- src/amd/vulkan/radv_shader.c | 2 +- src/amd/vulkan/radv_shader.h | 8 ++++---- src/amd/vulkan/radv_shader_info.c | 22 +++++++++++----------- 4 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9e4f1882f3d..4aebe72956b 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -167,15 +167,15 @@ radv_generate_pipeline_key(const struct radv_device *device, const struct radv_p if (subgroup_size) { if (subgroup_size->requiredSubgroupSize == 32) - key.subgroups[s].required_size = RADV_REQUIRED_WAVE32; + key.stage_info[s].subgroup_required_size = RADV_REQUIRED_WAVE32; else if (subgroup_size->requiredSubgroupSize == 64) - key.subgroups[s].required_size = RADV_REQUIRED_WAVE64; + key.stage_info[s].subgroup_required_size = RADV_REQUIRED_WAVE64; else unreachable("Unsupported required subgroup size."); } if (stage->flags & VK_PIPELINE_SHADER_STAGE_CREATE_REQUIRE_FULL_SUBGROUPS_BIT) { - key.subgroups[s].require_full = 1; + key.stage_info[s].subgroup_require_full = 1; } } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 04200944cfa..c441f2ac001 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -330,7 +330,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_ const struct radv_pipeline_key *key, bool is_internal) { unsigned subgroup_size = 64, ballot_bit_size = 64; - const unsigned required_subgroup_size = key->subgroups[stage->stage].required_size * 32; + const unsigned required_subgroup_size = key->stage_info[stage->stage].subgroup_required_size * 32; if (required_subgroup_size) { /* Only compute/mesh/task shaders currently support requiring a * specific subgroup size. diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index f5dfa27a644..12042740e43 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -55,9 +55,9 @@ enum radv_required_subgroup_size { RADV_REQUIRED_WAVE64 = 2, }; -struct radv_required_subgroup_info { - uint8_t required_size : 2; /* radv_required_subgroup_size */ - uint8_t require_full : 1; /* whether full subgroups are required */ +struct radv_shader_stage_key { + uint8_t subgroup_required_size : 2; /* radv_required_subgroup_size */ + uint8_t subgroup_require_full : 1; /* whether full subgroups are required */ }; struct radv_ps_epilog_key { @@ -92,7 +92,7 @@ struct radv_pipeline_key { uint32_t enable_remove_point_size : 1; uint32_t unknown_rast_prim : 1; - struct radv_required_subgroup_info subgroups[MESA_VULKAN_SHADER_STAGES]; + struct radv_shader_stage_key stage_info[MESA_VULKAN_SHADER_STAGES]; uint32_t storage_robustness : 2; uint32_t uniform_robustness : 2; uint32_t vertex_robustness : 2; diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index a9d956dfdcd..96474244b4e 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -339,10 +339,10 @@ assign_outinfo_params(struct radv_vs_output_info *outinfo, uint64_t mask, unsign static uint8_t radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, - const struct radv_required_subgroup_info *required) + const struct radv_shader_stage_key *stage_key) { - if (required->required_size) - return required->required_size * 32; + if (stage_key->subgroup_required_size) + return stage_key->subgroup_required_size * 32; if (stage == MESA_SHADER_GEOMETRY && !info->is_ngg) return 64; @@ -360,13 +360,13 @@ radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const stru static uint8_t radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, - const struct radv_required_subgroup_info *required) + const struct radv_shader_stage_key *stage_key) { if (stage == MESA_SHADER_COMPUTE && info->cs.subgroup_size) return info->cs.subgroup_size; - if (required->required_size) - return required->required_size * 32; + if (stage_key->subgroup_required_size) + return stage_key->subgroup_required_size * 32; return 64; } @@ -722,10 +722,10 @@ gather_shader_info_cs(struct radv_device *device, const nir_shader *nir, const s * is enabled. */ const bool require_full_subgroups = - pipeline_key->subgroups[MESA_SHADER_COMPUTE].require_full || + pipeline_key->stage_info[MESA_SHADER_COMPUTE].subgroup_require_full || (default_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics && local_size % RADV_SUBGROUP_SIZE == 0); - const unsigned required_subgroup_size = pipeline_key->subgroups[MESA_SHADER_COMPUTE].required_size * 32; + const unsigned required_subgroup_size = pipeline_key->stage_info[MESA_SHADER_COMPUTE].subgroup_required_size * 32; if (required_subgroup_size) { info->cs.subgroup_size = required_subgroup_size; @@ -978,9 +978,9 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n break; } - const struct radv_required_subgroup_info *req = &pipeline_key->subgroups[nir->info.stage]; - info->wave_size = radv_get_wave_size(device, nir->info.stage, info, req); - info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info, req); + const struct radv_shader_stage_key *stage_key = &pipeline_key->stage_info[nir->info.stage]; + info->wave_size = radv_get_wave_size(device, nir->info.stage, info, stage_key); + info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info, stage_key); switch (nir->info.stage) { case MESA_SHADER_COMPUTE:
