Module: Mesa Branch: staging/23.2 Commit: f9360a71844b96c5bb588fdfec9e99b9d0a23b16 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9360a71844b96c5bb588fdfec9e99b9d0a23b16
Author: Rohan Garg <[email protected]> Date: Fri Jul 14 12:15:33 2023 +0200 iris: migrate WA 14013910100 to use the WA framework Fixes: eeb3f4594d5 ("intel/xehp: Implement XeHP workaround Wa_14013910100.") Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24156> (cherry picked from commit 83716b08cf103622829d84e673584781ee8850f6) --- .pick_status.json | 2 +- src/gallium/drivers/iris/iris_state.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 98dcaa4398a..946285d850d 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -34,7 +34,7 @@ "description": "iris: migrate WA 14013910100 to use the WA framework", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "eeb3f4594d5acc40c1febf22f97ddb51517a0c88", "notes": null diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 49a922d40ec..2abd5ec87b0 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -430,6 +430,7 @@ flush_before_state_base_change(struct iris_batch *batch) static void flush_after_state_base_change(struct iris_batch *batch) { + const struct intel_device_info *devinfo = batch->screen->devinfo; /* After re-setting the surface state base address, we have to do some * cache flusing so that the sampler engine will pick up the new * SURFACE_STATE objects and binding tables. From the Broadwell PRM, @@ -467,7 +468,7 @@ flush_after_state_base_change(struct iris_batch *batch) * units cache the binding table in the texture cache. However, we have * yet to be able to actually confirm this. * - * Wa_14013910100: + * Wa_16013000631: * * "DG2 128/256/512-A/B: S/W must program STATE_BASE_ADDRESS command twice * or program pipe control with Instruction cache invalidate post @@ -478,7 +479,7 @@ flush_after_state_base_change(struct iris_batch *batch) PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_STATE_CACHE_INVALIDATE | - (GFX_VERx10 != 125 ? 0 : + (intel_needs_workaround(devinfo, 16013000631) ? 0 : PIPE_CONTROL_INSTRUCTION_INVALIDATE)); }
