Module: Mesa Branch: main Commit: ed9886321cec8cb077cd33543daa887bd49b296d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed9886321cec8cb077cd33543daa887bd49b296d
Author: Francisco Jerez <curroje...@riseup.net> Date: Tue Oct 24 15:24:18 2023 -0700 intel/xehp+: Use TBIMR tile box check in order to avoid performance regressions. This allows the hardware to behave as if TBIMR was disabled until a polygon is processed which spans at least one tile. This is a rather heavy-handed heuristic meant to prevent regressions in heavily geometry-bound workloads that render large numbers of tiny primitives much smaller than a TBIMR tile. A particularly bad example of this was observed in SoTR, where certain draw calls with a long-running VS and a mostly trivial PS render more triangles than pixels, filling up the URB and TBIMR batch pretty quickly, which causes EU utilization to tank (since once the URB has filled up the parallelism of the VS is limited by the number of polygons that fit in a TBIMR batch at the completion of each tile walk, which isn't a lot in relation to the total EU count of a DG2), and causes the bottleneck to be the rate at which the tile sequencer performs additional tile passes, each one processing a small number (<1024 polygons) of the hundreds of thousands of triangles of the draw call. Enabling this heuristic seems effective at avoiding that scenario in SoTR among other titles (e.g. Total War Warhammer 3), but it's a bit of a compromise since one could imagine cases where TBIMR is helpful even if the geometry doesn't pass the box check, so a better heuristic or a driconf rule may be useful in the future. Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25493> --- src/gallium/drivers/iris/iris_state.c | 1 + src/intel/vulkan/anv_private.h | 1 + src/intel/vulkan/genX_gfx_state.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index e0e540e12e3..206cb4f63c5 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6768,6 +6768,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, tbimr.VerticalTileCount = DIV_ROUND_UP(cso_fb->height, tile_height); tbimr.HorizontalTileCount = DIV_ROUND_UP(cso_fb->width, tile_width); tbimr.TBIMRBatchSize = util_logbase2(batch_size) - 5; + tbimr.TileBoxCheck = true; } } } diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 3e5dfabecd4..3bb8c5918f2 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1439,6 +1439,7 @@ struct anv_gfx_dynamic_state { unsigned VerticalTileCount; unsigned HorizontalTileCount; unsigned TBIMRBatchSize; + unsigned TileBoxCheck; } tbimr; bool use_tbimr; diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index c3d791268cd..d2cd30dfbe0 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -1280,6 +1280,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) DIV_ROUND_UP(fb_width, tile_width)); SET(TBIMR_TILE_PASS_INFO, tbimr.TBIMRBatchSize, util_logbase2(batch_size) - 5); + SET(TBIMR_TILE_PASS_INFO, tbimr.TileBoxCheck, true); SET(TBIMR_TILE_PASS_INFO, use_tbimr, true); } else { hw_state->use_tbimr = false; @@ -1891,6 +1892,7 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer) SET(tbimr, tbimr, VerticalTileCount); SET(tbimr, tbimr, HorizontalTileCount); SET(tbimr, tbimr, TBIMRBatchSize); + SET(tbimr, tbimr, TileBoxCheck); } } #endif
