Module: Mesa Branch: main Commit: e017bcae59ace7972e35571974d32b25c3381cd5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e017bcae59ace7972e35571974d32b25c3381cd5
Author: Caio Oliveira <caio.olive...@intel.com> Date: Tue Oct 31 09:53:30 2023 -0700 intel/compiler: Clarify the asserts in nir_load_workgroup_id lowering For Task/Mesh WorkgroupID is now lowered to WorkgroupIndex by the generic NIR pass, so we shouldn't hit this. We can now simplify the asserting code in emit_work_group_id_setup(). Reviewed-by: Ivan Briano <ivan.bri...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25977> --- src/intel/compiler/brw_fs.cpp | 14 +++++--------- src/intel/compiler/brw_fs_nir.cpp | 4 +++- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 74840c93107..80f844fa9c3 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -8059,21 +8059,17 @@ brw_compile_fs(const struct brw_compiler *compiler, fs_reg fs_visitor::emit_work_group_id_setup() { - assert(gl_shader_stage_uses_workgroup(stage)); + assert(gl_shader_stage_is_compute(stage)); fs_reg id = bld.vgrf(BRW_REGISTER_TYPE_UD, 3); struct brw_reg r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD)); bld.MOV(id, r0_1); - if (gl_shader_stage_is_compute(stage)) { - struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD)); - struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD)); - bld.MOV(offset(id, bld, 1), r0_6); - bld.MOV(offset(id, bld, 2), r0_7); - } else { - unreachable("workgroup id should not be used in non-compute stage"); - } + struct brw_reg r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD)); + struct brw_reg r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD)); + bld.MOV(offset(id, bld, 1), r0_6); + bld.MOV(offset(id, bld, 2), r0_7); return id; } diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 34df9a8f436..add1f62afae 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -194,7 +194,9 @@ emit_system_values_block(nir_block *block, fs_visitor *v) case nir_intrinsic_load_workgroup_id: case nir_intrinsic_load_workgroup_id_zero_base: - assert(gl_shader_stage_uses_workgroup(v->stage)); + if (gl_shader_stage_is_mesh(v->stage)) + unreachable("should be lowered by nir_lower_compute_system_values()."); + assert(gl_shader_stage_is_compute(v->stage)); reg = &v->nir_system_values[SYSTEM_VALUE_WORKGROUP_ID]; if (reg->file == BAD_FILE) *reg = v->emit_work_group_id_setup();
