Module: Mesa Branch: main Commit: 5de5a0d475505af2346214bfb2511bbe57139ce0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5de5a0d475505af2346214bfb2511bbe57139ce0
Author: Caio Oliveira <caio.olive...@intel.com> Date: Mon Nov 20 23:17:12 2023 -0800 intel/compiler: Don't use fs_visitor::bld in thread payload classes Reviewed-by: Ian Romanick <ian.d.roman...@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26301> --- src/intel/compiler/brw_fs.h | 4 ++-- src/intel/compiler/brw_fs_thread_payload.cpp | 15 +++++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 02919a44ece..2e53d682ee9 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -121,7 +121,7 @@ struct tes_thread_payload : public thread_payload { }; struct gs_thread_payload : public thread_payload { - gs_thread_payload(const fs_visitor &v); + gs_thread_payload(fs_visitor &v); fs_reg urb_handles; fs_reg primitive_id; @@ -154,7 +154,7 @@ protected: }; struct task_mesh_thread_payload : public cs_thread_payload { - task_mesh_thread_payload(const fs_visitor &v); + task_mesh_thread_payload(fs_visitor &v); fs_reg extended_parameter_0; fs_reg local_index; diff --git a/src/intel/compiler/brw_fs_thread_payload.cpp b/src/intel/compiler/brw_fs_thread_payload.cpp index 5197639dc42..31e6f30030a 100644 --- a/src/intel/compiler/brw_fs_thread_payload.cpp +++ b/src/intel/compiler/brw_fs_thread_payload.cpp @@ -99,17 +99,18 @@ tes_thread_payload::tes_thread_payload(const fs_visitor &v) num_regs = r; } -gs_thread_payload::gs_thread_payload(const fs_visitor &v) +gs_thread_payload::gs_thread_payload(fs_visitor &v) { struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(v.prog_data); struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(v.prog_data); + const fs_builder bld = fs_builder(&v, v.dispatch_width).at_end(); /* R0: thread header. */ unsigned r = reg_unit(v.devinfo); /* R1: output URB handles. */ - urb_handles = v.bld.vgrf(BRW_REGISTER_TYPE_UD); - v.bld.AND(urb_handles, brw_ud8_grf(r, 0), + urb_handles = bld.vgrf(BRW_REGISTER_TYPE_UD); + bld.AND(urb_handles, brw_ud8_grf(r, 0), v.devinfo->ver >= 20 ? brw_imm_ud(0xFFFFFF) : brw_imm_ud(0xFFFF)); r += reg_unit(v.devinfo); @@ -415,7 +416,7 @@ cs_thread_payload::load_subgroup_id(const fs_builder &bld, } } -task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v) +task_mesh_thread_payload::task_mesh_thread_payload(fs_visitor &v) : cs_thread_payload(v) { /* Task and Mesh Shader Payloads (SIMD8 and SIMD16) @@ -437,6 +438,8 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v) * the address to descriptors. */ + const fs_builder bld = fs_builder(&v, v.dispatch_width).at_end(); + unsigned r = 0; assert(subgroup_id_.file != BAD_FILE); extended_parameter_0 = retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD); @@ -444,12 +447,12 @@ task_mesh_thread_payload::task_mesh_thread_payload(const fs_visitor &v) if (v.devinfo->ver >= 20) { urb_output = brw_ud1_grf(1, 0); } else { - urb_output = v.bld.vgrf(BRW_REGISTER_TYPE_UD); + urb_output = bld.vgrf(BRW_REGISTER_TYPE_UD); /* In both mesh and task shader payload, lower 16 bits of g0.6 is * an offset within Slice's Local URB, which says where shader is * supposed to output its data. */ - v.bld.AND(urb_output, brw_ud1_grf(0, 6), brw_imm_ud(0xFFFF)); + bld.AND(urb_output, brw_ud1_grf(0, 6), brw_imm_ud(0xFFFF)); } if (v.stage == MESA_SHADER_MESH) {
