Module: Mesa
Branch: staging/23.3
Commit: e56220a3a5d75d1fdcae7d1a808cb20708d58bcb
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e56220a3a5d75d1fdcae7d1a808cb20708d58bcb

Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date:   Thu Nov 30 11:06:55 2023 +0100

radv: fix bogus interaction between DGC and RT with descriptor bindings

pipeline_is_dirty was never TRUE because it's emitted in the before
helper. This might fix bad interactions between DGC and RT because
they both use compute shaders and descriptor bindings need to be
re-emitted.

Found by inspection.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26417>
(cherry picked from commit ab6cf1592fc5c83a45709e68bceee9eb0e7d7870)

---

 .pick_status.json                |  2 +-
 src/amd/vulkan/radv_cmd_buffer.c | 23 ++++++++++++-----------
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 6952b34293f..2dcac119a9c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -374,7 +374,7 @@
         "description": "radv: fix bogus interaction between DGC and RT with 
descriptor bindings",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index fc8736bcf6d..cdede679552 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -9891,6 +9891,7 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer 
*cmd_buffer)
 {
    struct radv_compute_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
    struct radv_shader *compute_shader = 
cmd_buffer->state.shaders[MESA_SHADER_COMPUTE];
+   bool pipeline_is_dirty = pipeline != 
cmd_buffer->state.emitted_compute_pipeline;
 
    /* We will have run the DGC patch shaders before, so we can assume that 
there is something to
     * flush. Otherwise, we just split radv_dispatch in two. One pre-dispatch 
and another one
@@ -9903,6 +9904,17 @@ radv_dgc_before_dispatch(struct radv_cmd_buffer 
*cmd_buffer)
    si_emit_cache_flush(cmd_buffer);
 
    radv_upload_compute_shader_descriptors(cmd_buffer, 
VK_PIPELINE_BIND_POINT_COMPUTE);
+
+   if (pipeline_is_dirty) {
+      /* Raytracing uses compute shaders but has separate bind points and 
pipelines.
+       * So if we set compute userdata & shader registers we should dirty the 
raytracing
+       * ones and the other way around.
+       *
+       * We only need to do this when the pipeline is dirty because when we 
switch between
+       * the two we always need to switch pipelines.
+       */
+      radv_mark_descriptor_sets_dirty(cmd_buffer, 
VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR);
+   }
 }
 
 static void
@@ -9917,17 +9929,6 @@ radv_dgc_after_dispatch(struct radv_cmd_buffer 
*cmd_buffer)
       radv_emit_shader_prefetch(cmd_buffer, compute_shader);
    }
 
-   if (pipeline_is_dirty) {
-      /* Raytracing uses compute shaders but has separate bind points and 
pipelines.
-       * So if we set compute userdata & shader registers we should dirty the 
raytracing
-       * ones and the other way around.
-       *
-       * We only need to do this when the pipeline is dirty because when we 
switch between
-       * the two we always need to switch pipelines.
-       */
-      radv_mark_descriptor_sets_dirty(cmd_buffer, 
VK_PIPELINE_BIND_POINT_RAY_TRACING_KHR);
-   }
-
    if (compute_shader->info.cs.regalloc_hang_bug)
       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
 

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